Browse Prior Art Database

Divided Counter for Multichannel Links

IP.com Disclosure Number: IPCOM000120531D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 146K

Publishing Venue

IBM

Related People

Gyllenhammer, CR: AUTHOR [+2]

Abstract

Many statistics for a data/communications link can be tracked. These statistics are used by the link controller to determine how the link is operating and to determine if any corrective or maintenance actions should be taken.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

Divided Counter for Multichannel Links

      Many statistics for a data/communications link can be
tracked.  These statistics are used by the link controller to
determine how the link is operating and to determine if any
corrective or maintenance actions should be taken.

      Usually many sets of statistics are kept to aid in determining
the operational level of a link.

      When a link is divided into sub-channels, much of the
statistical information must be gathered at the sub-channel level to
provide the most usable information.

      Some examples of possible statistical counts that might be kept
are:
      The number of data transfers over a sub-channel during a set
period of time;
      The number of errors detected on information during a set
period of time;
      The number of specific types of information transferred during
a set period of time (for example, voice traffic or data traffic).

      Hardware counters start to present a problem when the link is
divided into many sub-channels.  Most communications interfaces
involve a single VLSI chip to control and monitor the link's
operation.  When multiple statistics are being recorded for multiple
sub-channels, the number of VLSI circuits that must be dedicated to
implementing counters becomes a problem.

      Often, all the desired statistics cannot be recorded because
the VLSI chip cannot hold all the circuits needed to implement all
the counters.

      Often, software routines are used to gather statistics. But
software routines require a microprocessor to dedicate some of its
processing power to running this software. Also, software operates
much slower than hardware and would have a difficult time handling
statistical information presented by the hardware at hardware speeds.

      This solution places the extra statistical information in
another VLSI chip.  This solution can handle the speeds that are
required, but it is a more costly solution in terms of development,
hardware costs, and adapter card area.

      The solution to this problem is to only implement part of the
counter in the hardware with an added status signal (or bit) and
place the rest of the counter in the support logic that already
exists to make the link operable.

      This type of division allows the external logic to operate at a
much slower speed because it does not have to count every event.

      For example, let us assume there was a 16-bit statistics
counter needed to count the errors detected per sub-channel.

      If the lower 8 bits of the counter were implemented in hardware
and the upper 8 bits were implemented in software, only half the
number of gates would be needed on the chip and the software routine
could run at a speed 256 times slower than the hardware (this number
comes from the fact that it would take 256 hardware cycles to cause
the 8 bit hardware counter to overflow).

      The operation of the Up and...