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LSSD Boundary-Scan Cell for IEEE Standard 1149.1

IP.com Disclosure Number: IPCOM000120540D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 31K

Publishing Venue

IBM

Related People

Keyser, FR: AUTHOR [+3]

Abstract

A level-sensitive scan design (LSSD) implementation of a boundary- scan cell is described that may be used as an input or output cell. This circuit meets all of the requirements of the IEEE standard. There is no path that is not tested by one or more of the instructions.

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LSSD Boundary-Scan Cell for IEEE Standard 1149.1

      A level-sensitive scan design (LSSD) implementation of a
boundary- scan cell is described that may be used as an input or
output cell.  This circuit meets all of the requirements of the IEEE
standard.  There is no path that is not tested by one or more of the
instructions.

      Referring to the figure, latch L1 is the master (L1) stage and
latch L2 is the slave stage of a master-slave (L1-L2) shift register
latch (SRL).

      Latch Ln may be an LSSD L1, L2*, or L3 latch.  An L1 (or
L2*) would have an additional port clocked by LSSD scan A (or B)
clock.  If Ln is an L3 latch, an LSSD shift P clock must be ORed
with UpdateClockBS.

      There are no inversions shown along the data path from either
data input to latch L1 through latch Ln, and through the system data
multiplexer M.  Actually, any even number of inversions may be used.