Browse Prior Art Database

8 X 5 Timer

IP.com Disclosure Number: IPCOM000120544D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 114K

Publishing Venue

IBM

Related People

Christianson, MD: AUTHOR [+2]

Abstract

An 8 X 5 timer uses a two-stage counter and multiplication to generate at least three usable timing functions. It employs available LSSD clocks and a minimal amount of logic in a simple, easy-to-understand, easily wirable, free-running timer design of minimal noise and timing delays.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

8 X 5 Timer

      An 8 X 5 timer uses a two-stage counter and
multiplication to generate at least three usable timing functions.
It employs available LSSD clocks and a minimal amount of logic in a
simple, easy-to-understand, easily wirable, free-running timer design
of minimal noise and timing delays.

      There are innumerable ways to design a timer, or counter,
circuit.  The design chosen will usually depend on the application in
which it is being used, the amount of available cell space, the
available input clocks, etc.  The application for which the 8 X 5
timer was originally designed called for an output pulse every two
microseconds.

      The available LSSD clocks had a period of 50 ns.  As such,
there are forty clock cycles in a two-microsecond period.  Rather
than simply counting forty clock pulses as a ripple counter would
essentially do, the 8 X 5 timer uses a multiplication function to
achieve the same result.  A 5-state machine can be combined with an
8-state machine to produce a 40-state machine.  Each individual state
of the 40-state machine will repeat itself only once every two
microseconds.  The resultant logic and wiring is much simpler than
that of most any other timer circuit.

      An 8-state machine will use three latches and possibly some
combinational logic, depending upon the implementation used.  The
state table in Fig. 1 was decided upon because it requires a minimum
of logic.  It is actually the combination of a 2-bit gray code
counter (bits B and C) and a third bit (bit A).

      The circuit consists only of the three latches and one 3-input
AND gate to feed the clock input to latch A (see Fig. 3).

      A 5-state machine will also consist of three latches and
possibly some combinational logic.  The state table in Fig. 2 was
decided upon because it requires a minimum of logic.

      The ci...