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Architecture for an Expert System Performance Analyzer

IP.com Disclosure Number: IPCOM000120551D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 154K

Publishing Venue

IBM

Related People

Stroebel, GJ: AUTHOR [+3]

Abstract

Disclosed is a general architecture for an expert system which analyzes multi-tasking computer system performance. At any given time, a multi-tasking system is performing a number of tasks for a number of different users. A single task utilizes a system resource or resources, and, when finished with those, moves on to other resources. When a job requires a new resource of the system, it may have to wait because that resource is being used by another job. When all goes well, jobs are able to access the resources they need and complete processing in reasonable time; however, sometimes the system becomes bogged down, so that jobs spend most of their time waiting for resources or performing unnecessary overhead processing, as opposed to doing productive work.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

Architecture for an Expert System Performance Analyzer

      Disclosed is a general architecture for an expert system
which analyzes multi-tasking computer system performance. At any
given time, a multi-tasking system is performing a number of tasks
for a number of different users.  A single task utilizes a system
resource or resources, and, when finished with those, moves on to
other resources.  When a job requires a new resource of the system,
it may have to wait because that resource is being used by another
job. When all goes well, jobs are able to access the resources they
need and complete processing in reasonable time; however, sometimes
the system becomes bogged down, so that jobs spend most of their time
waiting for resources or performing unnecessary overhead processing,
as opposed to doing productive work.  The performance analyzer
described herein is designed to diagnose the causes of these
problems.

      The analyzer must have access to data generated during one or
more performance intervals; this data may be gathered by the analyzer
itself or a separate data gathering program. The analyzer starts its
task with a mountain of performance data, and progressively narrows
the scope of its inquiry to the data it deems most significant.  The
advisor is divided into three levels of analysis, designated EXP0,
EXP1 and EXP2.  EXP0 is the user interface level.  From an
architectural standpoint, its function is to filter intervals, i.e.,
EXP0 will select some subset of the intervals in the user's
performance database for analysis. This selection is passed on to the
next level (EXP1), which then treats the selected subset as the only
intervals contained in the database.  EXP1 is the high-level
analysis; its function is to determine which portion or portions of
the system appear to be causing performance bottlenecks and to invoke
the appropriate detailed analysis module at the next level (EXP2).
EXP1 does not discard data in the same way that EXP0 does, but its
effect is similar.  By deciding that a performance bottleneck exists
in some portion of the system, and invoking the detailed analysis
module for that portion, the scope of the inquiry has effectively
been narrowed.  The EXP2 level contains the detailed analysis. While
it is architecturally a "level", it consists of separate code modules
for each area of the system that may require analysis.  Its function
is to perform detailed analysis of a particular subsystem for a set
of intervals, and to generate conclusions about the cause of any
perceived performance bottlenecks and recommendations for their
solution.  While the function of each such module is the same in
high-level terms, the actual code is vastly different.  For example,
one such module may analyze CPU performance problems, another may
analyze problems associated with a storage subsystem, while still
another may analyze a communications subsystem.  This architecture is
diagrammed in the figure.

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