Browse Prior Art Database

Simple DRAM Support for Microcontrollers

IP.com Disclosure Number: IPCOM000120552D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 130K

Publishing Venue

IBM

Related People

Lemaire, CA: AUTHOR [+2]

Abstract

A method of connecting large-capacity Dynamic Random Access Memory (DRAM) to a microprocessor is disclosed. Memory select is generated, a virtual address is created and DRAM refresh signals are provided using software and a small amount of hardware logic.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Simple DRAM Support for Microcontrollers

      A method of connecting large-capacity Dynamic Random
Access Memory (DRAM) to a microprocessor is disclosed.  Memory select
is generated, a virtual address is created and DRAM refresh signals
are provided using software and a small amount of hardware logic.

      Typical computer DRAM interfaces include address multiplexers,
a delay module and control logic.  The address multiplexers divide
the large computer address into DRAM Row and Column address.  The
delay module is needed for DRAM timing which usually does not
synchronize with system clocks, and the extra control logic is needed
to tie the whole design together.  (An example of address
multiplexers, a delay module and control logic can be found in the
IBM Personal Computer.)  And virtual addressing (mapping small
computer address spaces to a larger memory system) typically includes
yet more hardware and software too complex for most hand-held
computing applications.  At this time we have not seen any hand-held
computers that use DRAM memory.

      Computer memory can be used for either data information,
computer instructions or both.  There are three problems to solve:
DRAM refresh, address mapping, and Row/Column address multiplexing.
We will first describe a solution which provides memory simply for
data (not instructions).

      SIMPLE MICROPROCESSOR DRAM INTERFACE FOR DATA ACCESSES: DRAM
refresh is the simplest of the three problems.  If the
microcontroller has internal timers, one of the timers can be set to
interrupt periodically and the microcontroller simply reads at least
one byte from each of the DRAM internal Rows within the total refresh
time specified by the memory manufacturer.  An example of this type
of refresh design is that used in the IBM Personal Computer.

      The second problem is to provide mapping for a large address
space (4 megabytes) into the typical 64K-byte address space that is
directly addressable by the microcontroller.  Assume we are using
eight 4meg by 1 bit memory modules (4meg by 8 bits).  These memory
components generally have 11 Row Address bits (2K Rows) and 11 Column
Address bits (2K Columns).  This allows the microcontroller to view
these memory modules as 2048 pages of 2048 bytes per page.

      We use software to convert this paging memory scheme into one
large linear address.  This is done with three registers (forming a
24 bit - 16 megabyte - address) and three software subroutines:
SETADDR, INCADDR and DECADDR. Once the address is loaded into the
registers, one call to SETADDR is required, which breaks the large
address down into Row and Column addresses, latches the DRAM page,
and initializes the microcontroller external memory address register.
A...