Browse Prior Art Database

Check Stop Mask Register

IP.com Disclosure Number: IPCOM000120560D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 34K

Publishing Venue

IBM

Related People

Hicks, DA: AUTHOR [+2]

Abstract

This invention describes a way to mask out certain check stop conditions. In the current RISC System/6000* design, a check stop can only be masked out for an entire chip. Thus, if one error condition needs to be masked off from the system, all other reporting errors will be masked off too. This article describes how error conditions can still be reported while not reporting certain specified errors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Check Stop Mask Register

      This invention describes a way to mask out certain check
stop conditions.  In the current RISC System/6000* design, a check
stop can only be masked out for an entire chip.  Thus, if one error
condition needs to be masked off from the system, all other reporting
errors will be masked off too. This article describes how error
conditions can still be reported while not reporting certain
specified errors.

      Different error conditions are recorded internally to the chip
in check stop registers.  These register bits are then ORed together
and dotted onto a system check stop line to report them to the
system.  If a mask is used to first gate these register signals
before they are ORed together, certain error conditions can be
'blocked' from the system check stop line.  Because the masking is
done before the ORing and not before the latch, the error conditions
are recorded but not reported.

      The OCS (Off Chip Sequencer) and COP (Common On-chip Processor)
can set the latch bits for the mask registers in the chip at POR
(Power On Reset) time to the required values.  Thus, with a ROS (Read
Only Storage) change, the values in the check stop mask register can
be controlled and selective errors can be masked off from the system.

      This will allow a 'simple' EC to the ROS to temporarily fix a
problem in one of the processor chips caused by a logic bug.
*  Trademark of IBM Corp.