Browse Prior Art Database

Modifiable Protected Mode Time Base for Performance

IP.com Disclosure Number: IPCOM000120589D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Manges, MG: AUTHOR [+3]

Abstract

Disclosed is a method that allows applications to maintain time via the timer interrupt, but not incur the expected performance degradation due to necessary processor mode switches to service the timer interrupt. This article pertains to environments where the processor is switched between real and protected modes to handle the timer interrupts.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Modifiable Protected Mode Time Base for Performance

      Disclosed is a method that allows applications to
maintain time via the timer interrupt, but not incur the expected
performance degradation due to necessary processor mode switches to
service the timer interrupt.  This article pertains to environments
where the processor is switched between real and protected modes to
handle the timer interrupts.

      As PC DOS applications grow in sophistication, the memory
needed to run these applications has also grown.  In many cases,
these memory requirements exceed the amount provided by DOS.  Thus,
newer execution environments have been developed that use the
advanced processors protected mode because of the need to access more
memory.  These environments include OS/2*, Microsoft Windows 3.0**
and DOS/extenders.

      Many programs are usually event-driven by an external event,
such as communication or timer interrupts.  These interrupts cause
the program to perform certain functions. The DOS/extender versions
of these resident programs generally get control in real mode through
an interrupt. The program then performs a processor mode switch into
protected mode so that the interrupt can be serviced by the
application.  After the interrupt is serviced, the processor is
switched back to real mode.

      The processor mode switching time could be from under 100
microseconds to several milliseconds for a round trip (real to
protected to real mode, or protected to real to protected mode).  In
a time critical environment, such as handling communications,
processor mode switches need to be kept to a minimum to ensure good
system performance and that other interrupts can be serviced within
the required amount of time.

      Resident applications frequently trap timer interrupts. This
allows these programs to either keep track of elapsed time or to
ensure that the program itself gets control at periodic intervals.
However, since timer interrupts occur at a frequent interval...