Browse Prior Art Database

Latch Circuit

IP.com Disclosure Number: IPCOM000120594D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Appelbaum, LH: AUTHOR

Abstract

Latch circuit keeps IBM System/370 I/O Channel Control Unit from disrupting Channel and Host activity if Channel Adapter card is missing.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 67% of the total text.

Latch Circuit

      Latch circuit keeps IBM System/370 I/O Channel Control
Unit from disrupting Channel and Host activity if Channel Adapter
card is missing.

      Powering-on the control Unit when the Channel Adapter Logic
Card is not properly plugged in will disrupt all operations on the
Channel and possibly on the entire Host Computer System until the
control unit is powered-off.

      The risk of this disruption occurring is much higher than with
previous Control Unit models because this model is designed to be
serviced by untrained customer personnel.  If such a disruption were
to occur, the control unit would continue to IML normally but would
not go online.  It could take many minutes to isolate the problem and
many more minutes to bring the system back up.
Description

      Referring now to the figure, while Power-On-Reset (from the
power supply) is low (active), Driver-Reset will be held low (active)
by the combination of R2 and a glitch-free, open-emitter driver, U2.
While active, Driver-Reset will keep the Channel Drivers from driving
regardless of the state of their signal inputs from the Logic Card
and will keep the Integrated Select-Out Bypass Relay bypassing the
Select-Out signal.

      If the Logic Card is properly plugged into its connector,
C+OPLI (an existing Channel Tag signal from the Logic Card) will be
low when Power-On-Reset goes high, causing Driver-Reset to be latched
high and the card to function normally.  When C+OPLI g...