Browse Prior Art Database

Clean State of MP Cache Lines for Software Control

IP.com Disclosure Number: IPCOM000120601D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 128K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

In conventional MP cache designs Valid bit (V-bit) is used to indicate whether a cache line is valid. When a cache line is modified (stored) by a remote processor, the system control (e.g., SCE) will be signaled XI-invalidate and the line will be marked invalid (e.g., with associate V-bit turned OFF). In various applications this may result in loss of concurrency. Certain techniques for software control of cache coherence (e.g., -*-) perform selected cache flushing conservatively. That is, a cache line may get flushed (invalidated) even when it is not contaminated. The benefit of such conservative flushing is the avoidance of individual XI-invalidate signaling, which is important for highly parallel MP.

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Clean State of MP Cache Lines for Software Control

      In conventional MP cache designs Valid bit (V-bit) is
used to indicate whether a cache line is valid.  When a cache line is
modified (stored) by a remote processor, the system control (e.g.,
SCE) will be signaled XI-invalidate and the line will be marked
invalid (e.g., with associate V-bit turned OFF).  In various
applications this may result in loss of concurrency.  Certain
techniques for software control of cache coherence (e.g., -*-)
perform selected cache flushing conservatively.  That is, a cache
line may get flushed (invalidated) even when it is not contaminated.
The benefit of such conservative flushing is the avoidance of
individual XI-invalidate signaling, which is important for highly
parallel MP.  In this invention we consider a more conventional
environment in which the SCE (or common bus) can still carry out
XI-invalidate signaling (e.g., when a line is first stored at a
cache).  However, a cache line need not be invalidated right away and
may still be accessible until a certain point.  We would like to
provide the capability of flushing only those actually contaminated
lines from a cache at a certain point via software protocols.  The
basic idea is to add a state to record the status of contamination at
cache directories.

      Consider an MP system with processors Pi(1&i&N).  Each
processor has its own cache Ci .  We assume that the system provides
certain protocol (instruction) CLEANUP, which will be used to make
sure that all contaminated lines are flushed out of the cache.  At
the cache directory, we assume an extra CLEAN state.  The state may
be represented in various ways.  In the following we assume that the
state is indicated with an explicit C-bit at each directory entry. We
also assume that the processor caches are store-thru (e.g., to L2 or
L3).  When a processor stores into a cache line (e.g., the 1st time
after the line is brought to the cache, as indicated by a
Local-Change type state), the system control (e.g., SCE or common
bus) makes sure that all remote caches that may contain the line get
notified properly.

      When a cache line is first fetched into a cache, the associated
C-bit is turned ON (meaning that it is up-to-date).  When the cache
control (e.g., BCE) at a processor receives a remote store signal on
a line L, it checks whether L is in its cache.  If so, the associated
C-bit is turned OFF (meaning that the line has been contaminated by
remote processors).  A cache line may be validly accessed by the
processor as long as it is valid (i.e., V-bit is ON), even when the
C-bit is OFF.  Upon the execution of a CLEANUP, all the valid lines
(with V-bit ON) in the executing processor cache are made invalid if
the corresponding C-bit is OFF.

      Related Issues

      (a)  The CLEANUP execution may be more efficiently carried out
by ANDing the corresponding V-bits and C-bits in multiplicity as bit
strings.

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