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Universal LSSD-Hardware Test Interface

IP.com Disclosure Number: IPCOM000120603D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 97K

Publishing Venue

IBM

Related People

Ambrico, L: AUTHOR [+5]

Abstract

Disclosed is a design for a level-sensitive scan design (LSSD) printed circuit card test interface. The test interface is controlled by an IBM Personal Computer (PC) and provides LSSD scan controls, clock controls, and a communication bus to the card. It is useful when debugging a new card design because it provides not only those traditional debug functions, like scanning, clock stopping and stepping, microprocessor stopping and single cycling, but also the added function of the communication bus. The communication bus uses a simple handshaking protocol to transfer user-defined commands and data between IBM PC and the printed circuit card. Fig. 1 shows a block diagram of the entire test set-up including the test interface.

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This is the abbreviated version, containing approximately 52% of the total text.

Universal LSSD-Hardware Test Interface

      Disclosed is a design for a level-sensitive scan design
(LSSD) printed circuit card test interface.  The test interface is
controlled by an IBM Personal Computer (PC) and provides LSSD scan
controls, clock controls, and a communication bus to the card.  It is
useful when debugging a new card design because it provides not only
those traditional debug functions, like scanning, clock stopping and
stepping, microprocessor stopping and single cycling, but also the
added function of the communication bus.  The communication bus uses
a simple handshaking protocol to transfer user-defined commands and
data between IBM PC and the printed circuit card.  Fig. 1 shows a
block diagram of the entire test set-up including the test interface.

      In the example shown in Fig. 1, provision is made for the test
interface by using a 40-pin connector.  The connector contains 26
signal pins and multiple ground pins for shielding purposes. (See
Fig.  2 for a list of the signal lines.)  An IBM PC adapter card was
designed using IBM 8255 programmable input/output devices and
standard components.  Finally, software was written to control the
adapter card.
Scan Control:

      The scan rings of all of the modules are tied together on the
card to form one scan ring.  The PC scans the data into and out of
a scan buffer in its memory.  Provision is made in the PC software to
extract the correct bits from the scan buffer and display them in the
correct format by hardware register names.  The designer can also
alter any bit in the scan buffer before scanning it back into the
card.
Clock Control:

      The PC can stop and step both the hardware and microprocessor
clocks on the card.  The card also provides statu...