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Clock Distribution Scheme With Minimal Frequency Spectrum

IP.com Disclosure Number: IPCOM000120613D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 86K

Publishing Venue

IBM

Related People

Hoffman, CR: AUTHOR

Abstract

Disclosed is a clock distribution method for a system of chips that must be synchronized to a single system clock. This method provides a way of controlling the timing skew of clock edges between different chips while, at the same time, eliminating all harmonic energy in the clock signal that propagates between the system chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Clock Distribution Scheme With Minimal Frequency Spectrum

      Disclosed is a clock distribution method for a system of
chips that must be synchronized to a single system clock. This method
provides a way of controlling the timing skew of clock edges between
different chips while, at the same time, eliminating all harmonic
energy in the clock signal that propagates between the system chips.

      Fig. 1A shows the essential components of the method. The OCD
(Off-Chip Driver) of chip 1 is a specially designed driver with an
output transition that has the shape of a raised cosine waveform
(Fig.  1B).  Therefore, the signal between chips has only the
fundamental clock frequency component.  This signal drives one input
of a high speed comparator C on both chip 1 and chip 2.  The second
input of each comparator is a voltage reference set to a
predetermined value for both chips.  By the choice of the voltage
reference value, specific timing intervals can be established.  For
example, assume a 50 MHz clock with the references set at (0.5 X
VDD), (0.8 X VDD), and (0.2 X VDD). The B CLK will have a transition
edge delay that trailed the positive-going edge of CLK by 2 ns and
preceded the falling edge of CLK by 2 ns; the C CLK will have a
positive-going edge that precedes the rising edge of CLK by 2 ns and
a falling edge that trails the CLK falling edge by 2 ns.

      The voltage reference is easily achieved by either a resistor
divider or a pair of diode-connected FETs, each in its own well in
order t...