Browse Prior Art Database

Phase-Frequency And Transition Detector Device

IP.com Disclosure Number: IPCOM000120614D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 117K

Publishing Venue

IBM

Related People

Soyuer, M: AUTHOR

Abstract

A new Phase and Frequency Detector (PFD) for use in timing recovery applications is described. When used as part of a Phase-Frequency Locked Loop circuit, the new circuit generates phase- and frequency- sensitive outputs which are activated by the positive and negative transitions in the Non-Return to Zero data signal. This, in turn, eliminates the need for additional phase and transition detector devices in timing recovery applications. The new PFD circuit design is based on the rotational frequency detection concept which is discussed in the prior art and literature [*]. One version of the new PFD circuit implementation is shown in Fig. 1. It uses four positive-edge triggered D-type flip-flops with outputs Q1, Q2, Q7 and Q8, four negative-edge triggered D-type flip-flops with outputs Q3, Q4, Q5 and Q6, as shown in Fig.

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Phase-Frequency And Transition Detector Device

      A new Phase and Frequency Detector (PFD) for use in
timing recovery applications is described.  When used as part of a
Phase-Frequency Locked Loop circuit, the new circuit generates phase-
and frequency- sensitive outputs which are activated by the positive
and negative transitions in the Non-Return to Zero data signal. This,
in turn, eliminates the need for additional phase and transition
detector devices in timing recovery applications. The new PFD circuit
design is based on the rotational frequency detection concept which
is discussed in the prior art and literature [*].  One version of the
new PFD circuit implementation is shown in Fig. 1.  It uses four
positive-edge triggered D-type flip-flops with outputs Q1, Q2, Q7 and
Q8, four negative-edge triggered D-type flip-flops with outputs Q3,
Q4, Q5 and Q6, as shown in Fig. 1(a), and six combinatorial logic
NOR/OR gates to create the frequency detector outputs UP and DOWN
from the sequential logic outputs, as shown in Fig. 1(b).  The input
data transitions sample the VCO signal and its quadrature to measure
the phase and frequency difference between the input signal and VCO.
The difference between two of the D-type flip-flop outputs, Q1 and
Q3, is used to create a phase detector output which is sensitive to
the positive and negative data transitions as shown in Fig. 1(a).

      For the purpose of the following discussion, the VCO cycles are
divided into quadrants A, B, C, and D as discussed in -*-.  In the
new PFD version shown in Fig. 1, the VCO quadrants A and D are used
for frequency detection, whereas the quadrants B and C are used for
phase detection. Therefore, there is a 180 phase difference between
the positive VCO transition and data transitions when phase lock is
achieved.  This, in turn, places the positive VCO transition in the
middle of the data window for optimum re-timing.  Frequency detector
outputs UP and DOWN are used to increase and decrease the VCO
frequency, respectively. Frequency detector output UP is activated
only when a data transition in A is followed by a data transition
with reverse polarity in D.  Frequency detector output DOWN is
activated only when a data transition in D is followed by a data
transition with reverse polarity in A.  The circuit operates such
that when the frequency lock...