Browse Prior Art Database

CMOS-To-ECL Level-Converter for 2.5 V BiCMOS Technology

IP.com Disclosure Number: IPCOM000120620D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR

Abstract

As CMOS-based BiCMOS technology evolves toward 0.25 mm features, it again presents a challenge for circuit designers to propose a high performance BiCMOS circuit family. In a 0.5 mm BiCMOS technology, conventional BiCMOS circuits suffer from speed degradation due to supply scaling to 3.3 volts. A circuit technique, level-shifting -*-, has been proposed for 0.5 mm BiCMOS circuits to improve speed leverage over CMOS by using a higher supply (3.3 + Vbe). In a 0.25 mm BiCMOS generation, it would be advantageous to be able to use a single, scaled CMOS supply for implementing bipolar/CMOS circuits. Thus, total chip power of a higher level of integration can be managed. But, for a 2.5 V operation, both the conventional and level-shifted BiCMOS circuits completely lose speed leverage over a scaled 0.25 mm CMOS.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

CMOS-To-ECL Level-Converter for 2.5 V BiCMOS Technology

      As CMOS-based BiCMOS technology evolves toward 0.25 mm
features, it again presents a challenge for circuit designers to
propose a high performance BiCMOS circuit family.  In a 0.5 mm BiCMOS
technology, conventional BiCMOS circuits suffer from speed
degradation due to supply scaling to 3.3 volts.  A circuit technique,
level-shifting -*-, has been proposed for 0.5 mm BiCMOS circuits to
improve speed leverage over CMOS by using a higher supply (3.3 +
Vbe).  In a 0.25 mm BiCMOS generation, it would be advantageous to be
able to use a single, scaled CMOS supply for implementing
bipolar/CMOS circuits.  Thus, total chip power of a higher level of
integration can be managed.  But, for a 2.5 V operation, both the
conventional and level-shifted BiCMOS circuits completely lose speed
leverage over a scaled 0.25 mm CMOS.  On the other hand, ECL circuit
has always been an alternative and is the fastest circuit in all the
BiCMOS generations.  But, it suffers from much higher power as well
as the difficulty of level conversion between a small ECL signal
(ZVbe or less) and a much higher full swing CMOS signal.

      Disclosed is a CMOS-to-ECL interface circuit technique along
with signal levels for a 0.25 mm BiCMOS technology.  A modified ECL
circuit is operated at its minimum supply (3 Vbe), i.e., Z 2.5 volts
of CMOS circuits, to reduce circuit power.  The communication between
the ECL and a CMOS circuit is realized by using a diode-shifted
BiNMOS converter.  A single supply of (3 Vbe) volts is chosen for
designin...