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ECL-to-CMOS Level-Converter for 2.5 V BiCMOS Technology

IP.com Disclosure Number: IPCOM000120621D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 100K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR

Abstract

As CMOS-based BiCMOS technology evolves toward 0.25 mm features, it again presents a challenge for circuit designers to propose a high performance BiCMOS circuit family. In a 0.5 mm BiCMOS technology, conventional BiCMOS circuits suffer from speed degradation due to supply scaling to 3.3 volts. A circuit technique, level-shifting -*-, has been proposed for 0.5 mm BiCMOS circuits to improve speed leverage over CMOS by using a higher supply (3.3 + Vbe). In a 0.25 mm BiCMOS generation, it would be advantageous to be able to use a single, scaled CMOS supply for implementing bipolar/CMOS circuits. Thus, total chip power of a higher level of integration can be managed. But, for a 2.5 V operation, both the conventional and level-shifted BiCMOS circuits completely lose speed leverage over a scaled 0.25 mm CMOS.

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ECL-to-CMOS Level-Converter for 2.5 V BiCMOS Technology

      As CMOS-based BiCMOS technology evolves toward 0.25 mm
features, it again presents a challenge for circuit designers to
propose a high performance BiCMOS circuit family.  In a 0.5 mm BiCMOS
technology, conventional BiCMOS circuits suffer from speed
degradation due to supply scaling to 3.3 volts.  A circuit technique,
level-shifting -*-, has been proposed for 0.5 mm BiCMOS circuits to
improve speed leverage over CMOS by using a higher supply (3.3 +
Vbe).  In a 0.25 mm BiCMOS generation, it would be advantageous to be
able to use a single, scaled CMOS supply for implementing
bipolar/CMOS circuits.  Thus, total chip power of a higher level of
integration can be managed.  But, for a 2.5 V operation, both the
conventional and level-shifted BiCMOS circuits completely lose speed
leverage over a scaled 0.25 mm CMOS.  On the other hand, ECL circuit
has always been an alternative, and is the fastest circuit in all the
BiCMOS generations.  But, it suffers from much higher power as well
as the difficulty of level conversion between a small ECL signal
(ZVbe or less) and a much higher full swing CMOS signal.  A basic 2.5
V ECL circuit with diode-shifted, partial-swing BiNMOS output driver
(Fig. 1) has been proposed in the preceding article.

      Disclosed is an ECL-to-CMOS level converter for 0.25 mm BiCMOS
technology.  A ECL-to-CMOS converter is realized by an ECL logic
circuit and a built-in CMOS inverter.  The inverter uses ECL
complementary outputs as high and low supplies.  As shown in Fig. 2a,
with a slight modification to one of the BiNMOS output buffers, i.e.,
interchanging D2 and N2 as compared to the D1 and N1 connection,
three output signals can be generated.  First, a signal across the
load resistor, swinging from Vdd to (Vdd-Vbe); second, a signal from
the emitter...