Browse Prior Art Database

Multi-Port Dynamic Random Access Memory Controller

IP.com Disclosure Number: IPCOM000120625D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 141K

Publishing Venue

IBM

Related People

Holley, EL: AUTHOR [+2]

Abstract

A multi-port dynamic random access memory (DRAM) controller architecture for microcomputer systems is described which permits multiple functional units to access memory or bus functional units independently. The controller provides separate control interactions to each bus functional unit without access limitations, thereby improving operational performance of the system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Multi-Port Dynamic Random Access Memory Controller

      A multi-port dynamic random access memory (DRAM)
controller architecture for microcomputer systems is described which
permits multiple functional units to access memory or bus functional
units independently.  The controller provides separate control
interactions to each bus functional unit without access limitations,
thereby improving operational performance of the system.

      Typically, the main memory in a microcomputer consists of a
DRAM connected directly to the address bus and the data bus through
the DRAM controller.  A DRAM controller provides access and timing
signals and the necessary DRAM refresh cycles.  Cycle stealing direct
memory access (DMA) (the delaying of memory access by the
microprocessor) may be added to permit access to the main memory by
functional units other than the microprocessor.  An alternative is
the use of a dual-port static random access memory (SRAM) which is
accessible by both the microprocessor and other functional units
requiring memory interaction.  However, limitations exist in both the
size of available dual-port SRAMs and limitations in the control of
the functional units, should both ports be accessed simultaneously.

      In prior art, other DRAM control mechanisms were available as
discrete logic, or implemented within a single integrated circuit
(IC), to provide automatic DRAM refresh. However, the mechanisms did
not provide multi-port access, arbitration for access, or spare cycle
refresh capability. The DRAM controller discussed herein can control
SRAM input/output (I/O) functional units, or a particular bus, by
simply disabling both refresh functional units.

      The concept described herein implements a multi-port DRAM
control to provide independent access from multiple buses, with
separate control interaction to each bus without access limitations.
Also, a spare cycle/demand cycle refresh implementation is provided.
A spare cycle/ demand refresh is a single functional entity which
selects the type of refresh (spare cycle or demand cycle) permitted a
particular time.  Each type of refresh is a separate functional unit.
The controller provides simultaneous high-speed access to the channel
attachment DRAM by means of a microprocessor, bus DMA and/or access
functional units. Significant performance improvement can be
realized, as compared to conventional DRAM access, through a single
path.

      The drawing is a functional block diagram which shows the
multi- port DRAM controller functional unit and the interconnections
to the ports.  The multi-port DRAM controller consists of the
following functional units: (The term 'port x' represents the port
number, 0, 1 or 2).
-   Port x address bus 10.  Provides the address bus signals from
each functional unit requiring access to the DRAM.
-   Port x address buffer 11.  Provides functional unit isolation of
each port address bus 10 from the DRAM address bus unt...