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Technique for Interfacing Microprocessors With Programmable Integrated Wait State Generators to External System Controllers

IP.com Disclosure Number: IPCOM000120629D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Lee, AK: AUTHOR [+4]

Abstract

This article describes a technique to operate a microprocessor peripheral with fixed wait state during the transient period between microprocessor reset and programming to a wait state matching that of the peripheral's capability. After reset, the microprocessor cannot recognize faster ready return from the peripheral.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Technique for Interfacing Microprocessors With Programmable Integrated
Wait State Generators to External System Controllers

      This article describes a technique to operate a
microprocessor peripheral with fixed wait state during the transient
period between microprocessor reset and programming to a wait state
matching that of the peripheral's capability.  After reset, the
microprocessor cannot recognize faster ready return from the
peripheral.

      Some microprocessors have programmable integrated wait state
generators to allow the external logic to work at different system
speeds.  On executing a reset operation, the microprocessors are
designed to start with a predetermined number of wait states.  The
problem occurs when the system is designed to run at a number of wait
states different from the predetermined number.  In this case, the
external logic has to compensate for the discrepancy.  Disclosed
herein is a scheme for matching the programmable wait states of the
microprocessor to the system controller (not shown).  This solution
allows the controller to work at a single number of wait states and
spare the complexity of a variable number of wait states in a single
controller.

      The solution of this disclosure allows controllers having a
fixed number of wait states to operate with the programmable wait
states of a microprocessor.  There are three signals which are
crucial to the functioning of this logic, the clock signal being sent
by the microprocessor (u_Clk), the clock for driving the external
circuit (Ext_Clk), and a signal controlling the logic which governs
the number of clocks being seen by the external circuit (Cntl_Sig).

      Fig. 1 shows a block diagram of the...