Browse Prior Art Database

Algorithm for Data Alignment On the Micro Channel

IP.com Disclosure Number: IPCOM000120630D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

The Micro Channel* Architecture requires masters and DMA controllers to perform dynamic data alignment on the Micro Channel during read and write operations. Disclosed is a novel algorithm by which this can be achieved with minimal hardware.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

Algorithm for Data Alignment On the Micro Channel

      The Micro Channel* Architecture requires masters and DMA
controllers to perform dynamic data alignment on the Micro Channel
during read and write operations.  Disclosed is a novel algorithm by
which this can be achieved with minimal hardware.

      For simplicity, assume a master contains an aligned 4-byte-wide
internal bus, B0-B3, which is used to transfer data to/from the Micro
Channel data bus, D3-D0.  The following is the algorithm for data
alignment during READ operations:
D0 to B0, if                              [CW=1 AND p=1]
D1 to B0, if            [CW=2 AND q=1] OR [CW=1 AND q=1]
D2 to B0, if                              [CW=1 AND r=1]
D3 to B0, if  [CW=4] OR [CW=2 AND y=1] OR [CW=1 AND s=1]
D0 to B1, if            [CW=2 AND q=1]
D2 to B1, if  [CW=4] OR [CW=2 AND y=1]
D1 to B2, if  [CW=4]
D0 to B3, if  [CW=4]
where  p = 1, if  (DS=4 AND A30=1 AND A31=1)
        q = 1, if  (DS=4 AND A30=1 AND A31=0)
        r = 1, if  (DS=4 AND A30=0 AND A31=1) OR (DS=2 AND A31=1)
   y = 1, if  (DS=4 AND A30=0 AND A31=0) OR (DS=2 AND A31=0)
        s = 1, if  (DS=1 OR y=1)
        A30 = Micro Channel Address bit 30
        A31 = Micro Channel Address bit 31
        SW  = 1, if  (Byte Count = 1)             OR  (A31=1)
            = 4, if  (Byte Count >=4) AN...