Browse Prior Art Database

Master Streaming Data Register File Access

IP.com Disclosure Number: IPCOM000120633D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

Streaming Data Protocol is a single address, multiple data protocol on the Micro Channel*. A Master is a device on the Micro Channel that arbitrates for the bus and generates the address and the control signals (read/write, etc.). The Master can transfer data using standard protocol or the Streaming Data Protocol. The latter is a faster protocol and has tighter timing requirements.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 90% of the total text.

Master Streaming Data Register File Access

      Streaming Data Protocol is a single address, multiple
data protocol on the Micro Channel*.  A Master is a device on the
Micro Channel that arbitrates for the bus and generates the address
and the control signals (read/write, etc.).  The Master can transfer
data using standard protocol or the Streaming Data Protocol.  The
latter is a faster protocol and has tighter timing requirements.

      In this application, the data to be transferred on the Micro
Channel by the Master using the Streaming Data protocol is stored in
two register files.  Each register file is 4 bytes wide and 16 words
long.  The register files are organized as 8 bytes by 16 words.  This
is shown in Fig. 1.  The data stored in the register files may be
read such that part of the data is accessed from one register file
and the other part from the second in the same cycle.  For example,
bytes CDEF are accessed in the first cycle and GHIJ are accessed in
the next cycle.  In Fig. 1, when the address changes to access GHIJ,
the delay is through the latch, incrementer (INC) and the multiplexer
(MUX).  This could be several nanoseconds.

      A faster implementation is shown in Fig. 2.  In this
implementation the incremented address is at the input of the MUX.
When the address changes to access bytes GHIJ, the MUX is switched
and the two addresses are latched.  This saves the delay through the
incrementer and the delay for switching the MUX...