Browse Prior Art Database

Use of Pre-Oriented Wafers at Normal Incidence for Ion Implantation

IP.com Disclosure Number: IPCOM000120646D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Lever, RF: AUTHOR [+2]

Abstract

It is common practice in the semiconductor industry to grow crystals close to a major crystal axis, such as <100> <110> or <111> and then cut the wafers so that their plane is normal to that axis. This avoids pattern offset after subsequent epitaxial growth, although a small (less than 3~) offset is sometimes used to prevent pattern 'wash-out.' Epitaxial pattern offset is not important when subcollectors are partitioned by trenching, as is now standard practice in many applications, or when a blanket subcollector is employed. It is also unimportant when photolithographic alignment is achieved by means other than sighting on the subcollector pattern.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Use of Pre-Oriented Wafers at Normal Incidence for Ion Implantation

      It is common practice in the semiconductor industry to
grow crystals close to a major crystal axis, such as <100> <110> or
<111> and then cut the wafers so that their plane is normal to that
axis.  This avoids pattern offset after subsequent epitaxial growth,
although a small (less than 3~) offset is sometimes used to prevent
pattern 'wash-out.' Epitaxial pattern offset is not important when
subcollectors are partitioned by trenching, as is now standard
practice in many applications, or when a blanket subcollector is
employed.  It is also unimportant when photolithographic alignment is
achieved by means other than sighting on the subcollector pattern.

      It is well known that ion implants should be made at least 4~
offset from the principal wafer axis, (e.g. <100>) to avoid undesired
channeling effects which not only give a usually undesired 'tail' in
the dopant profile but also render that profile very difficult to
repeat in an accurate and reproducible manner.  This is presently
done for <100> wafers by tilting the wafer at approximately 7~ offset
from the <100> direction at an azimuthal angle designed to avoid both
<100> axial and {400} and {200} planar channeling.

      For some purposes, an even larger tilt than the standard 7~
would be desirable, but excessive 'shadowing' would result.  For
future technology, where lateral dimensions can be comparable to or
even smaller than the vertical thickness of the lithographic
patterning hardware, even a small offset such as 4~ could well cause
an unacceptable amount of 'shadowing.'  'Shadowing' refers, of
cou...