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Browse Prior Art Database

iAPX 80386 Erratum Workaround

IP.com Disclosure Number: IPCOM000120648D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Rasmussen, EC: AUTHOR

Abstract

This article describes a method of circumventing an erratum in the Intel 80386 B1 stepping level microprocessor. The erratum can cause improper operation whenever page translation is enabled (flat model, segmentation on paging, or virtual 8086 mode). This workaround applies to the flat model.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

iAPX 80386 Erratum Workaround

      This article describes a method of circumventing an
erratum in the Intel 80386 B1 stepping level microprocessor.  The
erratum can cause improper operation whenever page translation is
enabled (flat model, segmentation on paging, or virtual 8086 mode).
This workaround applies to the flat model.

      In an 80386 computer system when paging is enabled, port I/O to
addresses in the range 1000h to FFFFh may access the wrong ports.  If
the I/O address matches the linear address of a page which is cached
in the translation lookaside buffer (TLB), the 80386 may corrupt the
port address.

      One possible workaround is simply to remove linear addresses in
the range 4K - 64K from the application address space.  This is
feasible for segmentation on paging, but is not practical for the
flat model nor for virtual 8086 mode. The typical practice is to
insure that bits 12-15 of the linear address equal bits 12-15 of the
physical address for pages with flat addresses in the range 4K - 64K.
This negates any I/O address corruption.  Unfortunately, it makes
page management much more complex.

      A flat model memory manager can circumvent this erratum more
easily by exploiting the feature that flat addresses need not equal
linear addresses.

      In a conventional system, the flat address space is identical
to the linear address space.  This puts the affected pages in the
application area as shown in Fig. 1.

      Referr...