Browse Prior Art Database

Efficient Power-Supply Decoupling Scheme for Dynamic Rams

IP.com Disclosure Number: IPCOM000120649D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 127K

Publishing Venue

IBM

Related People

Dennard, RH: AUTHOR

Abstract

Described is a power-supply decoupling arrangement within a dynamic RAM memory chip which can efficiently handle large current surges during the sensing and rewriting of data. Noise on the internal voltage line, normally associated with the change of current flowing through the inductance of the power lines entering the chip, is avoided.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Efficient Power-Supply Decoupling Scheme for Dynamic Rams

      Described is a power-supply decoupling arrangement within
a dynamic RAM memory chip which can efficiently handle large current
surges during the sensing and rewriting of data. Noise on the
internal voltage line, normally associated with the change of current
flowing through the inductance of the power lines entering the chip,
is avoided.

      Typically, during the time when all the bit lines in a DRAM
chip are being charged or discharged, a large current surge flows
from the power supply VDD and into the ground terminal.  This current
surge flowing through the inductance L, which represents the
inductances in the power supply network bringing power into the chip,
can cause a voltage drop
                             L di
                               dt
 across the inductances and a corresponding fluctuation in
 the internal voltage levels on the VDD and ground lines
 within the chip.

      This fluctuation can be minimized to some extent by a
decoupling capacitance Cdec on the internal power supply bus which
occurs naturally or which can be specifically enhanced.  Relatively
large values of Cdec will cause the current surges to flow from the
stored charge in Cdec rather than through the inductances L to the
external power supply.  The charge is restored to Cdec from the power
supply at a slower rate over a period.

      The proposed improved arrangement of this article relates to a
DRAM chip in which the internal operating voltage is lower than the
external supply voltage.  This is a common situation in the 16-Mb
DRAM chips today where a 5 V external supply is used -*-.  For the
present discussion an internal voltage substantially lower than the
external supply voltage is considered, e.g., 3.5 V internal versus 5
V external.  The proposed power distribution system on the chip is
shown in Fig. 1, which is similar to that of -*-, except for how the
sense-amplifier power circuit is done.

      The proposed power arrangement for driving the sense amplifiers
is shown in Fig. 2.  The sense amplifier latches are activated by
switches S1 and S2 .  Typically both bit lines of a balanced sensing
arrangement are precharged to a voltage approximately halfway between
VINT and ground (or zero).  Each sense amplifier latch acts in such a
way as to discharge one bit line to ground while charging the other
one to VINT .  In the proposed arrangement of Fig. 2, all the charge
required to drive one bit line in each pair of bit lines to VINT
comes from the decoupling capacitance Cdec. This decoupling
capacitance is initially charged to VP, where VP = VINT + WV.  Cdec
is slowly charged between cycles through a current limiting circuit
which may also include a regulator.  For an external supply v...