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Programmable Single Bit Error Counter for Computer Error Checking And Correction Facilities

IP.com Disclosure Number: IPCOM000120663D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 92K

Publishing Venue

IBM

Related People

Blackledge, J: AUTHOR [+3]

Abstract

Described is a programmable single bit error counter (SBEC) to be used to track single bit errors in computers equipped with error checking and correction (ECC) facilities.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Programmable Single Bit Error Counter for Computer Error Checking
And Correction Facilities

      Described is a programmable single bit error counter
(SBEC) to be used to track single bit errors in computers equipped
with error checking and correction (ECC) facilities.

      Generally, the ECC computer facility provides single error
correction and double error detection.  Since single bit errors are
correctable, a number of single bit errors may occur without
interrupting the computer system.  An indication that single bit
errors have occurred is needed to insure the reliability of the
system.  A hard error that is always corrected would go undetected
without a single bit error indicator.  Since ECC is often used to
mask soft errors (transient errors), it is desirable to know if a
hard error is being masked.  A counter can provide information
regarding the frequency of single bit errors and can be used as a
diagnostic aid.  The programmable trigger level can be used to
generate an interrupt if the counter reaches a preset number, or the
counter can be polled periodically and reset.

      While there are other methods of tracking single bit errors,
such as using a counter with a fixed trigger level, or using a time
limit between soft errors, these other methods cannot be as flexible
as a counter with a programmable trigger level.  Using a counter for
single bit ECC errors, equipped with a programmable trigger level,
will insure memory subsystem reliability.

      The concept described herein provides an SBEC which monitors
the number of correctable errors detected.  The trigger level for the
SBEC is programmable through software, such that when the SBEC equals
the specific trigger level, a bit is set in a register and an
interrupt is generated to the system.  The SBEC can be read to
determine the number of errors that have occurred if the trigger is
not used.  The SBEC can be set, cleared, disabled, or enabled at any
point during system operation.

      The SBEC for single bit errors generates an interrupt and sets
the single bit interrupt status bit whenever a programmable limit is
reached.  If the SBEC is enabled, it increments each time a single
bit error is detected, except during scrub cycles.  Scrub cycles
occur if a single bit error has occurred.  A scrub cycle reads from
the failing memory location, corrects the data and writes back the
corrected data.  A scrub cycle is run to eliminate transient single
bit errors which exist in memory and were detected on a previous
memo...