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Efficient Normalizing/Denormalizing Unit for Floating Point Arithmetic

IP.com Disclosure Number: IPCOM000120670D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 27K

Publishing Venue

IBM

Related People

Fry, RE: AUTHOR [+2]

Abstract

The following describes an efficient execution unit design for normalizing and denormalizing floating point numbers that requires NO control logic.

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Efficient Normalizing/Denormalizing Unit for Floating Point Arithmetic

      The following describes an efficient execution unit design for
normalizing and denormalizing floating point numbers that requires NO
control logic.

      Figure 1 shows the block diagram of the normalizing/
denormalizing unit.  The entire unit takes only a few functional
blocks.  The critical path, LZD-sft_cntl-Shifter, can be done in only
13 and-or levels of logic.  The only control signal used is simply
the most significant bit of the inputted fraction; if this bit is a
one, the unit will denormalize the input; if it is a zero, the input
will be normalized.

      Disclosed anonymously.