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Prorammmable Processor Bus to MMIO Bus Dirigible Bus Mapping Control

IP.com Disclosure Number: IPCOM000120676D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 48K

Publishing Venue

IBM

Related People

Boldt, GD: AUTHOR [+2]

Abstract

This describes a design that permits a system processor to access the MMIO (Main Memory Input Output) bus using LOAD and STORE commands. This design directly maps the MMIO bus address range into the processor bus address range. The system processor can thereby treat the MMIO bus as if it were part of its own address space.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 76% of the total text.

Prorammmable Processor Bus to MMIO Bus Dirigible Bus Mapping Control

      This describes a design that permits a system processor to
access the MMIO (Main Memory Input Output) bus using LOAD and STORE
commands.  This design directly maps the MMIO bus address range into
the processor bus address range.  The system processor can thereby
treat the MMIO bus as if it were part of its own address space.

      This design increases the system's flexibility so that multiple
bus masters can be attached to a single processor bus.  This requires
that the bus masters be able to choose where the MMIO bus is to be
mapped onto the processor bus address space.

      This design also permits attachment to an MMIO bus which has
more than 24 addresses.  A more general version of this design would
also include a register specifying the starting MMIO address that the
processor bus range will be mapped to.

      It also includes the processor bus LOAD/STORE slave state
machine and an MMIO bus master state machine.  These state machines
respond to the processor's LOAD/STORE command signal sequences and
generate appropriate MMIO bus control signal sequences.

      Although reverse bus mapping need not be implemented, it is
possible to have both buses mapped onto one another in a similar
manner.  If both buses are mapped to each other, care must be taken
to avoid problems that might occur, e.g., bus lock up, when a bus
master such as a processor accesses the processor...