Browse Prior Art Database

High-Speed Decode And Redundancy Method for Semiconductor Memory

IP.com Disclosure Number: IPCOM000120677D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 52K

Publishing Venue

IBM

Related People

Williams, T: AUTHOR

Abstract

NOR decoders, non-interlocking timing, and localized tru/complement (T/C) generation are used to make a two-stage decode system which provides redundancy and achieves high-speed decoding or element substitution at low power.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 75% of the total text.

High-Speed Decode And Redundancy Method for Semiconductor Memory

      NOR decoders, non-interlocking timing, and localized
tru/complement (T/C) generation are used to make a two-stage decode
system which provides redundancy and achieves high-speed decoding or
element substitution at low power.

      Wordline decoding is shown in the figure.  Global address bus
A, from standard address buffer 2, passes throughout a memory chip.
For normal decoding of large arrays, primary NOR decoders 4 activate
a block of secondary decoders 4 associated with a block of array
wordlines 6. Decoders 4 generate the complement address and are gated
by global timing signals derived from chip enable and address
transition detection for asynchronous operation.

      Selection of a normal wordline element within block 6 results
in activation of localized T/C generators and decoders.  Localized
T/C generation keeps power and noise generation low.  Block decoding
allows use of high-speed NOR decoders throughout the array, charging
and discharging only primary and secondary decoders in a selected
block.

      Redundant operation is performed in parallel with block 6
selection.  Fuse comparators within circuit block 8 monitor global
address bus A and provide inputs to single stage, redundant NOR
decoder/driver 10.  A matched output from 8 indicates activation of
redundant word lines in redundant element block 12.  A disable signal
from circuit 10 is then sent via line D to deco...