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Browse Prior Art Database

Fully Testable High Performance Adder

IP.com Disclosure Number: IPCOM000120679D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 40K

Publishing Venue

IBM

Related People

Bechade, RA: AUTHOR [+2]

Abstract

A high performance adder circuit is described in which all stuck faults that can affect delay performance and DC function are testable with DC patterns.

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This is the abbreviated version, containing approximately 100% of the total text.

Fully Testable High Performance Adder

      A high performance adder circuit is described in which all
stuck faults that can affect delay performance and DC function are
testable with DC patterns.

      The least significant bit portion of the adder is shown in the
upper part of the figure.  When test input T1 is held high, output
signal SUM0 is the binary sum of inputs A0, B0, and CARRY INPUT.

      Three signals, CA, CO, and CS, are carried to the next bit.  If
carry select signal CS is 0, carry-AND signal CA is used as the carry
signal to the next stage.  Or, if select signal CS is 1, carry-OR
signal CO is the carry input to the next stage.

      Similarly, for each bit i, when test input T2 is held high,
output SUMi is the binary sum of Ai,Bi, and the carry input CA or CO,
selected by CS.

      With T1 held high for normal operation, carry signals CA and CO
cannot achieve the state CA = 1, CO = 0.  However, for complete
testing of downstream logic, CA = 1, CO = 0 is necessary.  Holding T1
to a low level allows this state to be achieved.

      Similarly, holding T2 to a low level allows outputs CA and CO
of bit i to achieve the state CA = 1, CO = 0, that otherwise
cannot be obtained.

      Disclosed anonymously.