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Time Delay Guide Pin

IP.com Disclosure Number: IPCOM000120692D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 41K

Publishing Venue

IBM

Related People

Herard, JD: AUTHOR [+2]

Abstract

Disclosed is a method which combines time delay features of guaranteed time delay for mating sequencing as well as a guidance feature which aids in pin alignment and helps prevent connector tilting which disrupts proper sequencing. The system is applicable to two-piece card-to-board connectors and cable-to-board connectors.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Time Delay Guide Pin

      Disclosed is a method which combines time delay features of
guaranteed time delay for mating sequencing as well as a guidance
feature which aids in pin alignment and helps prevent connector
tilting which disrupts proper sequencing. The system is applicable to
two-piece card-to-board connectors and cable-to-board connectors.

      The invention is comprised of a guide pin 2 which guides the
mating of the two halves of the connector and a time delay elastomer
pad or "doughnut" 1 which goes around the guide pin.

      As the two connector halves 3 and 6 are mated, guide pin 2
mates with receiving hole in receptacle 3.  At a predetermined point
between the engagement (using a given first pin level 4 and a given
second pin level 5) the receptacle body engages the elastomeric
deceleration pad 1. A force is required to compress pad 1.  This
force must be exerted by the receptacle 3.  The force results in
deceleration of the engagement of the connector, providing a
specified time delay between the engagements of the given first pin
level 4 and the given second pin level 5.  This delay feature is
critical to systems employing certain types of active board channel
maintenance features.  The design is adaptable to many current
connector designs.

      Disclosed anonymously.