Browse Prior Art Database

New Method for Burn-In of Large I/O Chips

IP.com Disclosure Number: IPCOM000120720D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 53K

Publishing Venue

IBM

Related People

Abrami, A: AUTHOR [+3]

Abstract

A new method to burn-in chips is disclosed which allows the use of MCP (Metallized Ceramic Package) substrates for chips which have a large number of I/O's. This method avoids the use of costly MLC (Multi-Layer Ceramic) substrates which would otherwise be required to burn-in such chips.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 68% of the total text.

New Method for Burn-In of Large I/O Chips

      A new method to burn-in chips is disclosed which allows the use
of MCP (Metallized Ceramic Package) substrates for chips which have a
large number of I/O's.  This method avoids the use of costly MLC
(Multi-Layer Ceramic) substrates which would otherwise be required to
burn-in such chips.

      Burn-in of bipolar chips is necessary to decrease field fails
and increase machine reliability.  In addition, single-chip burn-in
requires full pin-out access to assure complete stress coverage of
all parts of the chip.  For high density circuit designs, full access
to the large number of I/O's requires the use of costly MLC
substrates and severely limits "free pins" for individual chip
temperature monitoring.

      The disclosed invention is an elegant and economic solution to
the problem of full pin-out access to large I/O chips.  In addition,
the disclosure has applications for in situ individual chip thermal
sensing as well as on package circuit termination.  In one approach,
a specially designed test chip is mounted on a low cost MCP substrate
along with the chip that is to be tested.  The test chip is used to
drive the large number of I/O's on the chip under test through metal
lines that run on top of the ceramic package. Connections to the MCP
pins are required only to provide power to the two chips and to run
the test chip.  The test chip could be designed to allow for a number
of different stressing approach...