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CMOS Circuits Which Operate Optimally at Room Temperature And Low Temperatures

IP.com Disclosure Number: IPCOM000120725D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 99K

Publishing Venue

IBM

Related People

Ludwig, T: AUTHOR [+5]

Abstract

This article describes a CMOS Room Temperature and Low Temperatures Circuit Family made with a submicron room temperature process that operates optimally at room temperature (RT) as well as at low temperatures (LT), such as 77oK. Present n-polysilicon gate CMOS circuits suffer under the fact that they do not operate optimally at 350oK and at 77oK or below simultaneously. The basic reason is the large threshold voltage shift due to carrier freeze-out in the buried channel of the p-channel device. This effect is more severe at channel lengths below 1 micrometer. For example, the threshold voltage of 0.5 micron p-channel devices changes from -.6 V at 350oK to -1.2 V at 77oK.

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CMOS Circuits Which Operate Optimally at Room Temperature And Low
Temperatures

      This article describes a CMOS Room Temperature and Low
Temperatures Circuit Family made with a submicron room temperature
process that operates optimally at room temperature (RT) as well as
at low temperatures (LT), such as 77oK.  Present n-polysilicon gate
CMOS circuits suffer under the fact that they do not operate
optimally at 350oK and at 77oK or below simultaneously.  The basic
reason is the large threshold voltage shift due to carrier freeze-out
in the buried channel of the p-channel device.  This effect is more
severe at channel lengths below 1 micrometer.  For example, the
threshold voltage of 0.5 micron p-channel devices changes from -.6 V
at 350oK to -1.2 V at 77oK.  In order to optimize standard CMOS
circuits for LN2 temperature, the p-devices have to be designed as
true complementary devices with p- poly gates which requires more
complicated process steps.  However, the circuit chips that are
optimized for 77oK operation do not have enough threshold voltage
margins (or noise margins) at room temperatures.

      This article provides a description of a new CMOS
Room-Temperature-Low-Temperature (RTLT) circuit family which will
take advantage of the freeze-out-induced threshold voltage shift in
p-channel devices of standard n-poly CMOS processes so that the same
circuit chip can be used for either 350oK or 77oK operation without
having to change the CMOS fabrication processes.  The CMOS RTLT
circuit family, illustrated in Figs. 1, 2, and 3, allows operating
CMOS circuits optimally at room temperature and at LN2 temperature.
Circuits with small loads can still be standard CMOS circuits, and
the loss of gate overdrive capability of the p-channel at low
temperatures can be compensated by a slightly wider p-channel device.
However, starting fro...