Browse Prior Art Database

Fault Tolerant Adder Design

IP.com Disclosure Number: IPCOM000120730D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 139K

Publishing Venue

IBM

Related People

Vetter, LS: AUTHOR

Abstract

A hardware fault in current adders results in immediate system outage. This article proposes a design change that would allow continued system operation by utilizing the adder half that is good.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fault Tolerant Adder Design

      A hardware fault in current adders results in immediate
system outage.  This article proposes a design change that would
allow continued system operation by utilizing the adder half that is
good.

      The following method varies from U.S. Patent 3,603,934 in that
it minimizes hardware control to only the adder portion and does not
include the operand registers.  Other fault tolerant designs require
duplication of the entire function with each portion utilizing full
checking, or to use a triplicated design with voting.  This article
calls for the addition of minimal hardware to allow continued
operation.

      The additional hardware is for cross gating the source operands
such that any half of the operand sources can be gated to either half
of the adder.  Carry functions are gated and captured to allow for
proper operation when in half-mode operation.  Adder results are
gated for proper reconstruction of the sum.

      Fig. 1 shows an overview of the adder design, in this case, a
2-byte adder.  The additional hardware shown is as follows:
      1.   Operand/sum gating.
           AND (A) and OR(O) circuits to control gating/cross gating
and fencing operations from the operand registers to the adder.  Also
added is the adder sum to result register gating.
      2.   Carry functions.
           Modifications of the carry logic are shown in Fig. 2.  The
principal ones are to detect and capture the carry functions between
halves and out of the most significant     bit position.
       3.  Controls.
           Additional controls to set the gating and cross gating of
operands, sum and carry functions.

      The total amount of additional hardware is dependent upon the
basic design.  If gating of the source operands to the adder already
exists, then only the cross gating function is added.  The sum to
result register is additional and would be accomplished by using
extend ports to the Result Register SRLs.

      The operation of the Fault Tolerant Adder is as follows:
1.   Normal Operation.   The operands are added, in normal fashion,
through the adder to the result register.  This would be a single
machine cycle operation.
2.   Error detected.  A fault is detected in one byte of the adder.
Normal good checking of the adder would identify the origin of the
fault to one byte.
3.   Error reporting.  The error sets the normal error repor...