Browse Prior Art Database

Floating Point Instruction Decode Optimized for Detecting Valid Operands

IP.com Disclosure Number: IPCOM000120734D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Fry, RE: AUTHOR [+2]

Abstract

Disclosed is a method to encode floating point instructions to facilitate the checking for register dependencies between the instruction to be executed and any instructions ahead of it in the execution pipeline. This method also facilitates the checking of operands for special numbers, such as NAN and infinity, and easily determines which operands are to be fed into the execution pipe.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Floating Point Instruction Decode Optimized for Detecting Valid Operands

      Disclosed is a method to encode floating point
instructions to facilitate the checking for register dependencies
between the instruction to be executed and any instructions ahead of
it in the execution pipeline.  This method also facilitates the
checking of operands for special numbers, such as NAN and infinity,
and easily determines which operands are to be fed into the execution
pipe.

      The number of register operands required to execute an IEEE
floating point instruction range from zero to three operands.
Floating point units which can execute a Multiply-Add primitive in
one cycle require three operands. Multiply, divide, add, subtract and
compare instructions require two operands and register-to-register
move and store instructions require only one operand.  Instructions
which set bits or fields in the status and control register require
no operands from the register file.

      The RISC System/6000* floating point arithmetic unit executes
twenty-two instructions.  These instructions are encoded into a six-
bit field, with the first three bits representing the operands which
will be used for that instruction.  Three operands may be read out of
the register file in one cycle.  These operands can then be ANDed
with a single bit from the instruction decode register to determine
if that operand is used for any particular instruction. This speeds
up the process of the control unit determining which operands are
valid when checking for data dependencies and special numbers.  The
following table gives the instruction encoding for the RISC
System/6000 floating point unit.
FLOATING POINT INSTRUCTION DECODE

      The A, C and B operands are encoded in the first three bits of
the instruction.
DECODE REGISTER BITS
0 1 2 3 4 5
                ...