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Structures And Method for Electrically Measuring Centerline Tolerance Between Photolithographic Mask Levels

IP.com Disclosure Number: IPCOM000120742D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 141K

Publishing Venue

IBM

Related People

Morris, DP: AUTHOR

Abstract

This invention is directed to a combination of electrical structures which permit direct measurement of centerline tolerance between photolithographic mask levels on an integrated circuit. The structures have electrical contacts which span across regions of different built- in potential. The measurement technique will be described in terms of using Schottky Barrier diode contact to silicon, such as PtSi, Ti, TiW, on an EPI region, and the other mask level corresponding either to conducting region (e.g., a p or n semiconducting region) of higher built-in potential or nonconducting region. The technique is not limited to silicon semiconducting materials.

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Structures And Method for Electrically Measuring Centerline Tolerance
Between Photolithographic Mask Levels

      This invention is directed to a combination of electrical
structures which permit direct measurement of centerline tolerance
between photolithographic mask levels on an integrated circuit.  The
structures have electrical contacts which span across regions of
different built- in potential. The measurement technique will be
described in terms of using Schottky Barrier diode contact to
silicon, such as PtSi, Ti, TiW, on an EPI region, and the other mask
level corresponding either to conducting region (e.g., a p or n
semiconducting region) of higher built-in potential or nonconducting
region.  The technique is not limited to silicon semiconducting
materials.

      The  centerline displacement is measured using two uniquely
designed Schottky barrier diode structures on which a number of
electrical measurements are made.  From these measurements the
centerline displacement can be calculated from the equation where d
is the displacement.

      From the measurement of four voltages VR, VL, VS and VB on
these structures, the displacement of the centerline, d, from the
nominal value of zero is determined by use of the following equation
derived below:

                            (Image Omitted)

L    defined in Figs. 1 and 2 is the length of the Schottky barrier
diode.
VR   is the voltage between anode R and cathode R of Fig. 1 when
current I (between 1 to 10 ua) is forced between anode R and cathode
R.
VL   is the voltage between anode L and cathode L of Fig. 1 when
current I is forced between anode L and cathode L.
VS   is a voltage measured on the structure of Fig. 1 in the
following manner.  Anode R and anode L are connected in common.
Cathode R and cathode L are connected in common.  A current I is
forced between the common anodes and the common cathodes. VS is the
voltage between the common anodes and the common cathodes.
VB   is a voltage measured on the structure of Fig. 2 in the
following manner.  Anode R and anode L are connected in common.
Cathode R and cathode L are connected in common.  A current I is
forced between the common anodes and the common cathodes.  VS is the
voltage between the common anodes and the common cathodes.
q    is the electronic charge
k    is Boltzmann's constant
T    is Kelvin temperature
APPENDIX
DERIVATION OF EQUATION 2 FOR d
DEFINITION OF TERMS

      The above equation will be derived for a displacement between a
mask level Q2 defining a metal contact region and Q1 defining Pt
region or a dielectric region.  In Figs. 1 and 2 the section of the
Q2 region labeled anode forms a Schottky barrier diode over an N epi
material.  The section of the Q2 regions not labeled anode form a PN
junction if it is over a Pt region or is a contact to a dielectric.
The Schottky barrier diode has a lower built-in potential, therefore
current passe...