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Browse Prior Art Database

Array Built-In Self-Test With Diagnostic Logic

IP.com Disclosure Number: IPCOM000120744D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 114K

Publishing Venue

IBM

Related People

Jaber, TK: AUTHOR

Abstract

One of the major disadvantages of Built-In Self-Test recent implementations in various designs has been its implementation as a GO-NOGO test with no diagnostic capability allowing the isolation of a failure to a particular segment of the logic. This article describes an Array Built-In Self-Test (ABIST) implementation with diagnostic logic that allows a diagnostic capability down to a single failing array bit.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Array Built-In Self-Test With Diagnostic Logic

      One of the major disadvantages of Built-In Self-Test
recent implementations in various designs has been its implementation
as a GO-NOGO test with no diagnostic capability allowing the
isolation of a failure to a particular segment of the logic.  This
article describes an Array Built-In Self-Test (ABIST) implementation
with diagnostic logic that allows a diagnostic capability down to a
single failing array bit.

      Background:  Testing chip embedded arrays has always been a
difficult test problem, mainly because of (1) lack of controllability
over the array input logic and (2) poor observability of the array
output logic.  The problem was made worse when the embedded arrays
became latch bound, rather than chip I/O bound, making it necessary
to scan in the array test vectors and creating a huge test data
volume problem necessitating larger tester storage and more expensive
memory.  To resolve these problems, ABIST techniques were developed
so that the test data was generated and applied directly onchip, and
test response was collected and compressed into a signature of a
Multiple Input Shift Register.  The test result was also monitored
through a chip Primary Output pin, but no "expect" data was stored,
thus avoiding the cost of larger tester memories. One of the main
problems of this ABIST approach is lack of diagnosibility.  If an
array failure is detected, it is almost impossible to isolate the
failure.  This article describes a diagnostic logic that allows
failure isolation of the array(s) under test.

      Description:  The logic, as shown in the figure on the next
page, requires that the array be as latch bound as possible.  If
logic exists between the Data Input Register and the array input,
this logic is sensitized to allow a one-to-one correspondence between
data input register bits and array inputs.  The same is true for the
array output and Data Output Register.

      The Data Input Registers receive deterministic array test data
through a MUX that blocks the normal scan input and selects the
output of a DAPG (De...