Browse Prior Art Database

Parity Handling by a Hardware Debugger

IP.com Disclosure Number: IPCOM000120748D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Bordovsky, JS: AUTHOR [+4]

Abstract

Programmers and engineers do not normally want to have to worry about calculating and setting parity whenever they alter a register or memory. Disclosed is a method by which a hardware debugger can allow a user to manually set parity, or will automatically calculate and set parity using a number of different, specified, parity algorithms.

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Parity Handling by a Hardware Debugger

      Programmers and engineers do not normally want to have to
worry about calculating and setting parity whenever they alter a
register or memory.  Disclosed is a method by which a hardware
debugger can allow a user to manually set parity, or will
automatically calculate and set parity using a number of different,
specified, parity algorithms.

      In order to make a computer reliable, it should have some means
of self checking built into it.  When data is stored in arrays and
registers, storing parity with that data, and then checking that
parity, is a means of continually monitoring the integrity of the
CPU.  In order to give the designers the maximum flexibility in their
designs, it is advantageous to allow them the option of choosing the
parity generation and checking logic that best fits the needs of each
instance.

      Normally programmers do not have access to parity in a
computer, nor do they want to be bothered by it.  However, a hardware
debugger can access parity if it is in an array or in a latch.  In
order to remove the concern of parity generation from the
programmers, there should be a method of allowing programmer
accessible data to be altered while 'hiding' the parity generation.

      Since there may be times when the logic designers want to test
the parity checking logic, there should also be a method of setting
bad parity if desired.

      The Engineering Support Processor (ESP) for...