Browse Prior Art Database

Mechanism to Avoid Hangs Between Two Priority Controls Sharing Resources

IP.com Disclosure Number: IPCOM000120762D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 97K

Publishing Venue

IBM

Related People

Cheng, FM: AUTHOR [+3]

Abstract

Disclosed is a mechanism to prevent priority "deadlock" situations between two priority controls which require access to a resource to complete an operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Mechanism to Avoid Hangs Between Two Priority Controls Sharing Resources

      Disclosed is a mechanism to prevent priority "deadlock"
situations between two priority controls which require access to a
resource to complete an operation.

      For instance, a large multiprocessor design may have a
plurality of CPUs in which each CPU has its own level 1 cache (L1C).
Every L1C accesses a level 2 cache (L2C) which is controlled by an L2
cache controller (L2CC).  The L2C accesses system main storage (MS).
A priority relationship exists between the Main Storage Controller
(MSC) and the L2 Cache Controller (L2CC).  The MSC receives and
queues requests from the I/O subsystem and from the L2CC for access
to Main Storage (MS), made up of several Main Storage Arrays (MSAs).
For performance reasons, I/O fetch type requests are received by the
MSC and are simultaneously sent to a MSA (to start the relatively
long MSA access period) and to the L2CC to determine if the data is
L2C resident (called a Cross Interrogation (XI) request).  The MSA is
made busy by the I/O fetch and will remain busy to other fetch-type
commands until the L2CC responds to the XI request.  The MSC priority
can still honor a L2CC LRU castout store request once the MSA fetch
access is done, even though the data transfer has not finished.  A
LRU castout store is the action required when new data must be
brought into L2C and the "Least Recently Used" mechanism points to a
changed entry to be replaced.

      The L2C design is a "Store into L2" where the L2C can have the
only copy of processor changed data.  If the data is unchanged, the
MSC will return the MSA copy of the data to I/O when a Miss response
is received.  The two normal XI responses are:  1) Hit in L2: the
data must come from L2C rather than MSA; and 2) No Hit (Miss): the
data in MSA can be used.  The L2CC queues requests from multiple
Central Processors (CPs) as well as the MSC XI requests.  I/O XI
requests do not cause the data in L2C to be replaced, but rather
determine whether or not the I/O command will work out of MSA or L2C.
However, CP requests will cause data to be brought into L2C if it is
not already resident.  Bringing new data into L2C from the MSA can
necessitate a castout from L2C if the LRU array points to an entr...