Browse Prior Art Database

Signaling Between Virtual Processors

IP.com Disclosure Number: IPCOM000120786D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 205K

Publishing Venue

IBM

Related People

Blandy, GO: AUTHOR [+5]

Abstract

In a multiple processor closely coupled configuration, a means is typically provided for one CPU to send a signal to any one of the other online CPUs. In the IBM System/370* architecture, this is accomplished with the Signal Processor (SIGP) instruction.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 33% of the total text.

Signaling Between Virtual Processors

      In a multiple processor closely coupled configuration, a
means is typically provided for one CPU to send a signal to any one
of the other online CPUs.  In the IBM System/370* architecture, this
is accomplished with the Signal Processor (SIGP) instruction.

      The conceptual model for accomplishing the signaling assumes
the target CPU cannot act upon the signal the instant it is
presented.  Instead, the request to accept the signal is made
pending, and any related parameters are placed in a buffer.  The
sending CPU is then free to continue execution with the next
instruction.  The receiving (target) CPU disregards the pending
request until certain conditions obtain, such as end-of-current
operation or enabled-for-external-interruptions.  At a point
appropriate for the pending signal (order), the target CPU accepts
and acts upon the request.
Virtual Considerations

      Several additional considerations apply when the machine
provides for the interpretation of signaling between virtual CPUs.
Most fundamentally, the existing real pending and buffering
facilities of the real CPU generally cannot be used; there is no way
to assure that a particular CPU will be dispatched to execute, and
reach a receptive point within, a particular virtual CPU.  Were such
buffering used, an additional read-out function would be required.
This function would allow the buffered conditions to be saved
(buffered in storage) in the event an undispatch action becomes
required prior to reaching a receptive point. Further, a restore
mechanism would be needed upon redispatch.

      Because of such considerations, machine handling of virtual CPU
signaling was previously confined (VM/370) to certain special
circumstances, notably when real CPUs were dedicated to virtual CPUs.
Otherwise, prior to the mechanism described here, a virtual SIGP
instruction caused control to change from the guest to the host.
Execution of the SIGP instruction, including any implied interruption
in the target CPU, was then provided by programmed means
(simulation).

      The mechanism described here buffers the request in a serially
reusable save area in storage associated with the target virtual CPU
before the request is made pending.  This solves the problem of
holding a SIGP-action request until the target CPU reaches a
receptive point.  The presence of the buffered request is indicated
by a bit, permitting any real CPU that is dispatched to execute the
virtual CPU to be aware of the pending request so that the request
may be recognized and acted upon for the virtual CPU at a suitable
point.  Typically, the host control program does not become involved
in the signaling among virtual CPUs when this mechanism is used.
The Signaling Process

      Specifically, the present mechanism extends the capability of
the existing Start Interpretive Execution (SIE) instruction of the
IBM ESA/370* architecture.  The SIE instruc...