Browse Prior Art Database

Design-For-Test Architecture

IP.com Disclosure Number: IPCOM000120804D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Oakland, SF: AUTHOR

Abstract

A very large-scale integrated circuit (VLSI) architecture is described which is optimized for component testing and for multi-component interconnect testing.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 63% of the total text.

Design-For-Test Architecture

      A very large-scale integrated circuit (VLSI) architecture
is described which is optimized for component testing and for
multi-component interconnect testing.

      Referring to the figure, component input/outputs (I/Os) are
divided into groups as follows:
      1.  Test Access Port (TAP) inputs and output
      2.  TAP level-sensitive scan design (LSSD) Test
          Function Inputs
      3.  System LSSD Test Function I/Os
      4.  Other Test-only I/Os
      5.  LSSD Scan-only I/Os
      6.  Combined System Data and LSSD Scan I/Os
      7.  Other (System Data) I/Os

      Group 1 provides signals to and from TAP logic, thereby
allowing operation in conformance to IEEE standard 1149.1.

      Because IEEE 1149.1 does not conform to LSSD clocking rules,
group 2 inputs allow the TAP logic to be operated in conformance with
LSSD rules.  Because these signals affect operation of TAP logic, the
IEEE standard does not allow them to be used during normal system
operation; only Tap interface signals may be used to control TAP
logic.  The LSSD Test Function Inputs must be held (to 0 or 1) for
normal operation.

      Group 3 consists of those signals that are Test Function I/Os
for LSSD testing but also are used for normal system operation.  An
LSSD clock input might be used as a system clock, for example.  Since
these I/Os are used for system operation, the IEEE standard...