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Browse Prior Art Database

Elimination of Circuit Line-Lifting

IP.com Disclosure Number: IPCOM000120805D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Glenning, JJ: AUTHOR [+4]

Abstract

Using the original seed metal layer as a photoresist etch-mask and adhesion-promotion layer, and as an in-situ blanket etch mask layer during dielectric etching, has been found to: (1) eliminate undercut etching and subsequent lifting of circuit lines; (2) decrease residual organic contaminants on the back sides of exposed circuit lines in critical bonding areas; (3) eliminate a seed metal/plated metal interface from the bonding side of critical bonding leads, thereby increasing the anticipated reliability of the bonded assembly; (4) improve product yield; and (5) eliminate a processing restriction on product design.

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Elimination of Circuit Line-Lifting

      Using the original seed metal layer as a photoresist
etch-mask and adhesion-promotion layer, and as an in-situ blanket
etch mask layer during dielectric etching, has been found to:
      (1) eliminate undercut etching and subsequent lifting of
circuit lines;
      (2) decrease residual organic contaminants on the back sides of
exposed circuit lines in critical bonding areas;
      (3) eliminate a seed metal/plated metal interface from the
bonding side of critical bonding leads, thereby increasing the
anticipated reliability of the bonded assembly;
      (4) improve product yield; and
      (5) eliminate a processing restriction on product design.

      On many thin film products the signal and/or ground plane
circuitry are/is formed by pattern electroplating Cu from a thin
metal seed layer which has been previously deposited by other means.
Following photopattern and electroplating process steps, sub-etching
of this thin, blanket seed metal electrically isolates circuit lines.
Windows are then etched in the dielectric using additional
photoresist processing.  These etched windows allow access to the
circuit metallurgy from the back side of the dielectric for chip and
card bonding attachment.  It was found that using this prior process
format allowed dielectric etch solution to penetrate beneath the
photoresist etch mask at the photoresist/dielectric interface and
undercut the dielectric beneath circuit lines near the window edge.
This was not a concern using earlier designs where the circuit line
was only attached on one side of the etched window, and the circuit
line tip cantilevered (free standing) into...