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Browse Prior Art Database

Delay Equations for Timing Analysis

IP.com Disclosure Number: IPCOM000120806D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Agrawal, BK: AUTHOR

Abstract

An algorithm is presented for obtaining delay equations from the circuit simulation data. The delay equations obtained are non-linear polynomial functions, F(C1,Tx), of the load capacitance and the input transition. The non-linear polynomial delay equations for different circuits of the same type are then used to obtain the switching threshold capacitance. The delay coefficients along with the threshold capacitance are the key to the VLSI timing analysis.

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Delay Equations for Timing Analysis

      An algorithm is presented for obtaining delay equations
from the circuit simulation data.  The delay equations obtained are
non-linear polynomial functions, F(C1,Tx), of the load capacitance
and the input transition.  The non-linear polynomial delay equations
for different circuits of the same type are then used to obtain the
switching threshold capacitance.  The delay coefficients along with
the threshold capacitance are the key to the VLSI timing analysis.

      The delays and transitions are approximated by using cubic
splines between each load interval for a fixed input transition.
Once the cubic splines have been formed for each fixed input
transition, the maximum allowable load capacitance is computed for
the given circuit.

      The maximum allowed load is the minimum capacitance which, if
applied to the circuit output, will produce the maximum allowed fixed
rising or falling transition at the output for a given circuit.  Once
the maximum load capacitance is known, the slope of the delay curves
is determined by using the cubic spline approximation.  The critical
point where the curve changes abruptly is found. If there is no such
critical point, then only one set of delay equations is sufficient to
describe the entire range of the load capacitances for the given
circuit.  If there is a critical point less than the maximum allowed,
then the load interval is divided into two separate sets of intervals
at the critical point.  Each interval is then treated as a separate
least-square problem, thus generating two sets of delay equations for
the circuit.

      We define a (n,m) data matrix, D, composed of the m columns of
the known data vectors.  The (m,1) unknown solution vector B is
sought which minimizes the standard Euclidian norm,  Y-DB , in the
least- square sense, where Y is the known (n,1) column vector
composed of the observed delay values.  m is the number of elements
required in the solution vector, which depends upon the general
behavior of the circuit and the type of the polynomial desired.

      The cubic splines can be used to interpolate the functions...