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Buried Device Contacts And Diffusion Sources

IP.com Disclosure Number: IPCOM000120807D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

El-Kareh, B: AUTHOR [+4]

Abstract

Self-aligned recessed contacts and diffusion sources substantially improve performance and reliability of MOSFET, bipolar, and Schottky barrier diode (SBD) devices. This is achieved by etching a hole in silicon, self-aligned to existing boundaries. By filling the hole with doped polysilicon, impurities out-diffused from polysilicon into single crystal silicon form a buried graded junction which reduces peak field at a MOSFET drain, the extrinsic source/drain resistance in MOSFETs, and the base resistance in bipolar structures. The buried junction can also be formed by angled ion implantation and the hole filled with metal, thus further reducing series resistances. In addition, large area SBDs are defined simultaneously by etching silicon in a region of appropriate dopant type and concentration and filling with metal.

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Buried Device Contacts And Diffusion Sources

      Self-aligned recessed contacts and diffusion sources
substantially improve performance and reliability of MOSFET, bipolar,
and Schottky barrier diode (SBD) devices.  This is achieved by
etching a hole in silicon, self-aligned to existing boundaries.  By
filling the hole with doped polysilicon, impurities out-diffused from
polysilicon into single crystal silicon form a buried graded junction
which reduces peak field at a MOSFET drain, the extrinsic
source/drain resistance in MOSFETs, and the base resistance in
bipolar structures.  The buried junction can also be formed by angled
ion implantation and the hole filled with metal, thus further
reducing series resistances.  In addition, large area SBDs are
defined simultaneously by etching silicon in a region of appropriate
dopant type and concentration and filling with metal.

      A cross-section through the drain of a MOSFET is shown in Fig.
1.  Field oxide 10, gate oxide 6, gate electrode 2, oxide (or other
insulator cap) 4, and spacer 19 are defined on substrate 8 using
conventional processing.  Drain contact region 12, which is
self-aligned to boundaries of adjacent oxide 10 and 19, is etched in
substrate 8.  In the case of polysilicon fill, polysilicon 14 is
deposited conformally and then etched back to a level near the
surface of adjacent oxide 6 and 10.  Polysilicon 14 can be doped in
situ by ion implantation after deposition.  The structure is then
subjected to an appropriate thermal treatment...