Browse Prior Art Database

Programmable Address Translation for Multi-Processor Systems

IP.com Disclosure Number: IPCOM000120810D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 150K

Publishing Venue

IBM

Related People

Eng, RC: AUTHOR [+4]

Abstract

Described is a technique and programmable address translation mechanism for multi-processor systems which selectively maps system bus ranges to the resources of a given processing unit.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Programmable Address Translation for Multi-Processor Systems

      Described is a technique and programmable address
translation mechanism for multi-processor systems which selectively
maps system bus ranges to the resources of a given processing unit.

      Typically, a multi-processor system consists of several
processing units connected in a manner which allows the processing
units to communicate and cooperate with each other so as to perform
tasks faster and more efficiently than using a single processor.
Since the way in which the processing units are connected depends on
the design of the processing units themselves, variations will occur
from integrally connected units to the peers on a common
communication link or bus. Continued

      In prior art, dual-ported designs using decode and
adder/subtracter functions were used in multi-processor systems.  The
design described herein simplifies the decode operations in that only
one set of decodes is required for resources.  This is because the
system bus addresses are changed to match the local address.  In
addition, the circuitry is less complex, since a static random-access
memory (SRAM) is used instead of using adder/subtracters. Also, the
software control of the resource allocation and address assignments
is such that access to portions of the resources can be dynamically
and flexibly controlled.

      The concept concentrates on the peer processor system on a
common bus and discusses the sharing of resources which are contained
within one or more of the processing units. The processing unit's
resources are assumed to respond to bus accesses by other units
within given ranges of bus addresses, as well as responding to direct
accesses by the processing unit which contains the resources.

      In a multi-processing system consisting of multiple peer
processing units on a common bus, one or more units can contain
resources which are accessible over the bus.  It is often desirable
to dynamically define the ranges of addresses over the bus to which
each unit's resources respond.  This allows the system to selectively
distribute the resources of several processing units across the range
of available bus addresses. It also allows each processing unit to
access the resources of the other units.  Therefore, a method must be
provided to allow the resources to respond to a variable bus address
range.  Also, if the processing unit which contains the resources
requires that all or specific ranges of resources not be accessible
over the bus dynamically, the method must provide a means of
selectively inhibiting bus accesses to the resource. The concept
described herein provides all of these functions.

      Fig. 1 is an an example of a processor unit to system bus
address map for three processing units A, B, and C. Parts of...