Browse Prior Art Database

Source of Error Indication Circuitry

IP.com Disclosure Number: IPCOM000120816D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 138K

Publishing Venue

IBM

Related People

Dvorak, TJ: AUTHOR [+5]

Abstract

This article describes a circuit arrangement for use in a system which is comprised of multiple autonomous units communicating over a common bus that provides a means for determining all units involved in a transfer of information over the bus in which an error was detected.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Source of Error Indication Circuitry

      This article describes a circuit arrangement for use in a
system which is comprised of multiple autonomous units communicating
over a common bus that provides a means for determining all units
involved in a transfer of information over the bus in which an error
was detected.

      A typical computer system can consist of multiple units
connected together by a system bus over which the units communicate
to transfer information.  When an error occurs on a bus transfer,
there is usually a method by which the unit which detects the error
can report the error to the system in order to allow the system to
handle the error in an orderly fashion.  For instance, if a system
check is detected by a card installed in a system, the card activates
a system bus signal called "-IO/CHCK" (which stands for "Channel
Check").  By activating -I/O CHCK, a system bus check can be reported
to the system.  Additional information must be provided in order for
the system to determine what caused the check.  The unit which
detected the check could be the one that caused the fault, or it may
be one or more of the other units involved in the bus transfer.

      In a system where reliable repair of a system check is
critical, such as a system which controls a line in a manufacturing
application, it is important that all possible sources of the check
be identified to service personnel.  They can then have the option of
replacing or repairing whatever units they wish, or possibly
replacing all units involved, if getting the application running
again quickly is imperative.

      The circuit arrangement disclosed herein is shown in Fig. 1.
It monitors the system bus activity of the unit on which it resides,
along with the signal on the system bus which is used to report a
check.  It keeps track of whether the unit was driving address and/or
data information on the current or previous system bus cycle and
latches that fact when a check (-I/O CHCK) occurs.  The output of the
circuit, -SOURCE/ERROR, will be active (low) if the unit was driving
the address or data lines when a bus transfer cycle has an error.

      The inputs to the circuit shown in Fig. 1 are:
      o    -IO/CHCK
           Active low channel check system bus signal. Indicates that
a unit in the system detected a system check (error).
      o    -ADL
           Active low address latch system bus signal. Indicates that
the address is valid for the system bus cycle in process.
      o    -CMD
           Active low command active system bus signal. Indicates
that the data transfer part of the system bus cycle is in process.
      o    -ADDR/EN
           Active low address enable signal.  Indicates that the unit
was driving the address lines on the system bus, and thus was the
sour...