Browse Prior Art Database

Memory Stress Card

IP.com Disclosure Number: IPCOM000120825D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Carpenter, B: AUTHOR

Abstract

This article describes a card which enables the RISC System/6000* test engineers to verify the design margins of the memory card controller chip and the two data multiplexer chips located on the memory cards. The card also allows the test engineers to verify the timing margins for each type of SIMM used on the memory card.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Memory Stress Card

      This article describes a card which enables the RISC
System/6000* test engineers to verify the design margins of the
memory card controller chip and the two data multiplexer chips
located on the memory cards.  The card also allows the test engineers
to verify the timing margins for each type of SIMM used on the memory
card.

      The memory stress card was developed in order to assist the
test engineers during testing of the RISC System/6000 memory cards.
The stress card installs between the SIMM and the memory card.  It
consists of multiple delay modules and controlling TTL logic.  This
allows the stress card to delay the leading and trailing edges of the
critical signals sent to the SIMMs.  It also has the ability to
decrease pulse width, delay the pulse, and delay data lines coming
from the DRAMs (this simulates slower DRAMs).  The waveforms in Fig.
1 illustrate the different stress options which can be incorporated
into the critical signals.

      The stress card (see Fig. 2) also allows easy use of a logic
analyzer by providing pins (both signal and ground) for each signal
going to and from the SIMM.  This allows the test engineer to readily
compare the normal "unstressed" signal to the actual signal being
stressed on the SIMM.
*  Trademark of IBM Corp.