Browse Prior Art Database

Fixed Length Pipelined Bus Protocol for Snoop Cache

IP.com Disclosure Number: IPCOM000120831D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 103K

Publishing Venue

IBM

Related People

Murata, H: AUTHOR [+3]

Abstract

Disclosed is a bus protocol to pipeline the snoop bus transfer cycles, under maintaining the snoop cache coherency without any pipeline flow disturbance. This protocol improves the bus bandwidth for a snoop memory bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fixed Length Pipelined Bus Protocol for Snoop Cache

      Disclosed is a bus protocol to pipeline the snoop bus
transfer cycles, under maintaining the snoop cache coherency without
any pipeline flow disturbance. This protocol improves the bus
bandwidth for a snoop memory bus.

      The snoop memory bus is usually pipelined by overlapping the
bus snoop cycle to the data transfer cycle of the previous access,
because the atomicity of bus snoop cycle is easily realized.  To
maximize the bus utilization, this pipelining method needs that the
bus snoop and the data transfer occupies the same number of bus
cycles.  This article describes the pipelined bus protocol to
maximally overlap consecutive memory accesses, under maintaining the
atomicity of the bus snoop cycle.

      Generally the bus snoop can be divided into the following four
phases:
1) Address/Command output by the requester.
2) Cache tag check and update by the others.
3) Tag check response by the others.
4) Cache tag update by the requester.

      Basically these phases are able to be overlapped among
continuous accesses (Fig. 1).  In  Fig. 1 each phase is assumed to
occupy one bus cycle.  In other words, phases 1-4 are able to be
fully pipelined.  However, this pipelined bus snoop needs wait cycles
when the accesses to the same cache line occur consecutively.
Starting the next bus snoop cycle before the cache tag update
completion for the former access causes the cache inconsistency.  In
this case, this...