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Cycle Time Optimization Subject to Performance Constraints

IP.com Disclosure Number: IPCOM000120851D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 6 page(s) / 223K

Publishing Venue

IBM

Related People

LaPotin, D: AUTHOR [+2]

Abstract

This article presents a practical approach for optimizing the clock period subject to physical and electrical constraints. The development is a general approach for optimizing skew and is applicable to a broad class of systems. It is a significant improvement on the basic method presented by (1) since practical physical constraints are considered.

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Cycle Time Optimization Subject to Performance Constraints

      This article presents a practical approach for optimizing
the clock period subject to physical and electrical constraints.  The
development is a general approach for optimizing skew and is
applicable to a broad class of systems.  It is a significant
improvement on the basic method presented by (1) since practical
physical constraints are considered.

      A synchronous digital system can be modeled as blocks of
combinational elements separated by edge-triggered latches.  The set
of latches is denoted by L = {l1 ....,ln}.  Let P denote the clock
period.

      The circuit can be modeled as a synchronous communication graph
G containing n vertices, one for each latch.  There is a directed
edge between vertex i and j if, at some time during the clock cycle,
there is a combinational logic path from li to lj .  Each edge has
weights Dij and dij which denote the largest and smallest
combinational logic delays between latch li and lj, respectively.
The set-up and hold times of a latch, li, are denoted by tSETUPi and
tHOLDi, respectively. The delay from the clock source to the latch li
is denoted by wi .

      The skew optimization problem can now be formulated. The first
constraint concerns double clocking.  It states that the signal from
latch li to latch lj through the fastest path should not race through
the circuit before the end of one clock period.  The equation can be
written as follows:

                            (Image Omitted)

      The second equation concerns zero clocking, i.e., the slowest
signal from latch li to latch lj should not arrive at latch lj later
than the end of one period.  The corresponding constraint is:

                            (Image Omitted)

      Frequently, there are constraints on the minimum and maximum
achievable clock delays.

      The optimization problem may be stated as follows:
      Find the smallest clock period P such that equations 1, 2, 3
and 4 are satisfied.
           SLP: minimize P subject to

      This disclosure builds upon the above formulation, where cycle
time optimization can be performed under one or more of the following
constraints:
      1.   Every latch in the system has a unique clock line.
           This mode is called the free mode.
      2.   Every chip has one clock pin (compressed mode).
      3.   Chips can have more than one clock pin but the
      number of clock pins available per chip is prespecified
      (cluster mode).

      4.   The total number of different clock offsets in the system
is prespecified.  Some chips may have a limited number of pins while
others may have no restriction.  The algorithm will automatically
distribute the total number of available clock offsets while
satisfying the requirements of the chips with limited clock pins...