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# Optimum CMOS LSSD Clock Distribution Scheme

IP.com Disclosure Number: IPCOM000120853D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 65K

IBM

## Related People

Desrosiers, B: AUTHOR [+4]

## Abstract

Disclosed is a LSSD clock distribution scheme which uses the same clock distribution in System Mode and in Test Mode, saving thereby a test clock distribution with the associated input pin. In this article, there is described the clock distribution of a single chip floating point unit. The clock generation is on the chip.

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Optimum CMOS LSSD Clock Distribution Scheme

Disclosed is a LSSD clock distribution scheme which uses
the same clock distribution in System Mode and in Test Mode, saving
thereby a test clock distribution with the associated input pin. In
chip floating point unit. The clock generation is on the chip.

A good clock distribution scheme for a LSSD design implies to
solve three problems:
1. How to maximize the duty cycle time with a minimum skew between
the clock?
2. How to control the clocks in case of the use of clock splitters?
3. How to minimize the circuit added to meet the LSSD design rules?

The answer to the first question is to use a clock splitter
just in front of the registers and a balanced lightly loaded clock
distribution. The clock splitter generates two opposite signals which
are guaranteed non-overlapped and the lightly loaded clock
distribution minimizes the skew over the chip.  The out-of-phase
output is indicated by the wedge on figure.

As to the second problem, the prior art approach to meet the
LSSD design rules is to add a 2-way AND gate to each clock splitter
output and to connect the free input of the AND gate to the Test
Clock. The registers connected to the clocks are free running (clock
not gated) to reach the maximum duty cycle time (see upper half of
figure).

Finally, if clock gated registers were needed to save silicon
(a free run...