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Cyclic Redundancy Checking Macro

IP.com Disclosure Number: IPCOM000120855D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Bredin, F: AUTHOR [+2]

Abstract

A design of a Cyclic Redundancy Checking Macro (CRC) used for error detection is disclosed thereunder.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 98% of the total text.

Cyclic Redundancy Checking Macro

      A design of a Cyclic Redundancy Checking Macro (CRC) used
for error detection is disclosed thereunder.

      For example, when data is transferred from a microcomputer to a
floppy disk, it is usual to add a "cyclic redundancy check character"
(CRCC) as a means for achieving error detection.

      CRCC are generated, bit after bit, from a circuit based on a
shift register associated to logical gates (XOR). A new CRCC is
originated, for every new single bit of data, at each clock cycle.

      In this article, the CRCC calculation is performed every eight
bits, from a pure combinatory circuit. The latest value of the CRCC
is being produced from the former value of the CRCC, updated by the
coming eight bits of data.

      CRCC computation assumes division by a 17-bit binary number.
The generating polynomial G(X) = X16 + X 12+ X 5+ 1 is used to
calculate the terms of the CRCC.

      It can be shown that the CRC macro can be implemented with
Exclusive OR blocks (X) only. Twenty-four two-input Exclusive ORs
(XOR2) are used.

      The "high level" schematic of the CRC macro is shown in Fig. 1.
Each block symbolizes a two-way Exclusive OR, except block 100 which
comprises three two-way Exclusive OR gates, as illustrated in Fig. 2.

      The advantages of the CRC macro are:
      1. It generates a 16-bit CRCC for every eight bits with pure
combinatorial circuits.
 2. Its design can be extended to othe...