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Simplified Local Interconnection Technique for Sram And Logic Semiconductor Structures

IP.com Disclosure Number: IPCOM000120860D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 108K

Publishing Venue

IBM

Related People

Chesebro, DG: AUTHOR [+3]

Abstract

A method is shown for local interconnection from polysilicon to silicon in a salicide process. The technique involves a selective tapering etch step without any additional film deposition and is fully borderless to diffusion edges (ROX edges) for compatibility with either oxide or nitride spacer processes.

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Simplified Local Interconnection Technique for Sram And Logic Semiconductor
Structures

      A method is shown for local interconnection from
polysilicon to silicon in a salicide process.  The technique involves
a selective tapering etch step without any additional film deposition
and is fully borderless to diffusion edges (ROX edges) for
compatibility with either oxide or nitride spacer processes.

      Within SRAM and logic circuits, it is frequently advantageous
to use polysilicon as an interconnection between diffused regions,
thereby avoiding the need to use contacts and metal interconnections
for local wiring.  There are numerous techniques to interconnect
polysilicon conductors to the single crystalline silicon substrate,
all requiring several additional processing steps and some
variability in the ability to make low resistance ohmic
interconnections.  Some of these require the deposition of selective
silicon to form local interconnections; this additional conductor
deposition has the propensity for introducing defects which can short
circuit elements and impact the yield of perfect chips.  Also, other
techniques produce salicide step coverage problems when near vertical
steps.

      The new interconnection method uses the standard processing
elements of a salicide technology with the addition of a mask and
etch step.  The process steps are as follows:
1. Follow normal process sequence up through polysilicon definition
(PC etch and resist strip).
2. Referring to Fig. 1, apply and define photoresist with image
openings overlaying polysilicon lines which are to be connected to
underlying silicon.  This requires designing polysilicon lines over
thin gate oxide regions so that there must be some oxide remaining
where the original polysilicon has been etched.  Typically, there is
/100 angstroms of remaining gate oxide after PC etch.
3. Using a highly selective etching process, e.g., / 30:1 polysilicon
to oxide etch ratio, etch through the polysilicon wi...