Browse Prior Art Database

Thin Small Outline Packages

IP.com Disclosure Number: IPCOM000120866D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Dombroski, EJ: AUTHOR [+3]

Abstract

Thin small outline packages (TSOPs) utilizing selective insulation of the leadframe can be used for memory products.

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This is the abbreviated version, containing approximately 100% of the total text.

Thin Small Outline Packages

      Thin small outline packages (TSOPs) utilizing selective
insulation of the leadframe can be used for memory products.

      To retain busbars and concurrently reduce packaging thickness
by a factor of 2.5, the wire bond loops over the busbars must be
reduced in height and limited within a very fine process window.
Such space constraints indicate the need for positive signal wire
loop isolation from the busbars.

      Fig. 1 shows a screened or stenciled coating applied
strategically at busbar jumper positions.  The applied dielectric is
selected from among a family of printed circuit board solder resist
(a heat curable thixotropic dielectric, typically one or two mils
thick).  Curing is concurrent with chip to lead frame lamination
cure.

      Fig. 2 is the same chip shown in Fig. 1 with the round
dielectric spots selectively placed by punching single- or
double-sided dielectric film similar to the chip attachment film.
With double-sided adhesive advantages, the wire can be routed to be
in contact and cured in a locked and pre-wedged bonding position for
greater stability.  The spots shown in Fig. 2 may also represent
micro-dispensed dielectric non-running or thixotropic electrical
grade paint.