Browse Prior Art Database

Improved Store-Thru Cache

IP.com Disclosure Number: IPCOM000120870D
Original Publication Date: 1991-Jun-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 200K

Publishing Venue

IBM

Related People

Brenza, JG: AUTHOR

Abstract

This invention relates to a two-level cache hierarchy for a multi- processor (MP) system. Each processor (CP) has a private L1 cache, whereas the L2 cache is shared by all the (N) processors. For data which may be changed by any CP, a current copy is maintained in both its private L1 cache and the shared L2 cache. To achieve this concurrence, any store operation to cache is executed at both the L1 and L2 caches (see Fig. 1). The two-level cache hierarchy is thus a store- thru L1, store-in L2. There are several problems with such a cache hierarchy, primarily due to the combined store traffic at L2 cache generated by all the CPs in the MP system. First, an L2 directory operation, required for each store request, becomes a serious traffic bottleneck. Second, pending storage request queues become excessive.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

Improved Store-Thru Cache

      This invention relates to a two-level cache hierarchy for
a multi- processor (MP) system.  Each processor (CP) has a private L1
cache, whereas the L2 cache is shared by all the (N) processors.  For
data which may be changed by any CP, a current copy is maintained in
both its private L1 cache and the shared L2 cache.  To achieve this
concurrence, any store operation to cache is executed at both the L1
and L2 caches (see Fig. 1).  The two-level cache hierarchy is thus a
store- thru L1, store-in L2.  There are several problems with such a
cache hierarchy, primarily due to the combined store traffic at L2
cache generated by all the CPs in the MP system.  First, an L2
directory operation, required for each store request, becomes a
serious traffic bottleneck. Second, pending storage request queues
become excessive. This necessitates expensive pending store buffers.
The buffers themselves become a problem since they must be searched
due to any fetch request to L2 cache by any CP. Any pending store
operations to a cache line must be completed prior to allowing a
fetch operation to that line. Delaying the fetch operations increases
the "storage penalty" and reduces the CP MIPS.  This invention avoids
the use of the L2 directory for L2 storage operations, thereby
eliminating the traffic bottleneck.  This avoids the need for
expensive, multiple copies of the L2 directory,  reduces the size of
the pending store queues and increases the MIPS.

      This invention is illustrated in Figs. 1, 2, 3 and 4. The
concept is as follows.  The L1 directory contains an entry for each
L1 cache line.  Each entry comprises an address data field and a
control data field.  For this invention some additional bits are
added to the control data field, the number being determined by the
set associativity of the L2 cache (i.e., 2 bits for 4-way, 3 bits for
8-way, etc.).  These additional bits store the encoded set
associative compartment (hence called a bin number) of the source L2
line in L2 cache from which an L1 line has been fetched.  A new entry
is made in the L1 directory at the time a new line is brought into
L1 cache.  If the requested data is exclusive, that is writeable,
then the E bit is set "on" in the directory control field and the L2
bin number bits are also stored in the L1 directory entry at this
time. The numeric value of the L2 bin number is determined by an
encoder of the L2 directory address compare outputs.  Whenever a CP
requests to perform a store operation, controls first read the L1
directory to perform a "store interrogate" operation to establish
proper store authority.  This is done by examining certain bits
within the control field of the L1 directory entry for the
corresponding cache data line.  If the CP had proper store authority,
then the change data may be stored into the L1 cache and a store
request transaction is prepared to forward the store request to L2
cache.  To do this the Ab...